Hi,
We are using the TI TXS0102 device on the MDIO interface between Xilinx Zynq Ultrascale+ and TI DP83867 PHY with TI TXS0102 device.
We are facing intermittent MDIO access failures. In fail case, the TI DP83867 device is driving the MDIO line, one clock cycle earlier than expected.
We have captured waveforms in the Passing case and Failing case at PHY end and would like to review if the TXS0102 device could be contributing to this behavior. Please advise if you have some inputs on this.
The block diagram of the implementation is shown in slide 2 of attached file.
The passing and failing waveforms at PHY end are also attached.
Note: As can been seen from the block diagram, we introduced a 100pF capacitor at the TXS102 MDC output to reduce overshoot on the MDC waveform and reduce droop.
With the 100pF capacitor present, as can be seen from the shared waveforms, we are not violating the PHY device MDIO setup/ hold timing specification of 10ns/10ns.
However from our testing we suspect the 100pF capacitor at the TXS102 MDC output is contributing to Phy driving the MDIO line one clock cycle earlier than expected in the fail case.
For testing purpose, we tested by retaining the TXS0102 and only removing the 100pF capacitor. In this case the MDIO access passed (Tested for 15000 read accesses of PHYID1 and PHYID2). Also tested across temperature from -50C to +65C.
- Please advise if you have some explanation why the presence of the 100pF capacitor on the MDC signal at TXS0102 output seems to be causing the PHY device to drive the MDIO line one clock cycle earlier than expected in the fail case?
MDIOinterfaceAccessIssueDebug_CaptureatPhyEnd_0.3a.pdf
Note: We are also discussing with TI DP83867 Expert, Evan Mayhew on this topic in below thread.
Also I have a query on the TXS0102 gate bias setting:
The SCES640I –JANUARY 2007–REVISED OCTOBER 2018, datasheet states on Pg 15:
"The VGATE gate bias of the N-channel pass transistor is set at approximately one threshold voltage (VT) above the VCC level of the low-voltage side."
- Is above statement correct? If above statement is correct, the N-channel pass transistor will be ON when VCC level of the low-voltage side signal is applied at the input. I dont believe this is true.
- In my case VCCA and VCCB of TXS102 is 3.3V. Is the gate bias set to 3.3V + VT??
I believe when 3.3V signal is applied on the TXS0102 input, in steady state the Pass transistor will be OFF. When 0V is applied on the TXS0102 input, the pass transistor will be ON with the VGS above the threshold.
- Kindly confirm if above understanding is correct and on the TXS0102 Gate bias setting?
Thanks
Louis
