Other Parts Discussed in Thread: TVP5158,
We need to voltage translate the +3.3V output of the TI TVP5158 Video Decoder to +1.8V to match an FPGA I/O. The 10 bit data is being clocked out of the TI TVP5158 at 108 MHz.
I would like to use the SN74AVC16T245 to translate the 10 data bits + clock. I have 4 questions
- The timing for VCCA = 1.8V, VCCB = 3.3V is tplh(min) = tphl(min) = 0.5ns and tplh(max) = tphl(max) = 7.4ns ( B to A ). But what is the channel to channel skew ?
- Is the channel to channel skew the same between the two groups of 8 ? For example is the skew for 1B1 to 1A1 the same as between 2B1 and 2A1
- The datasheet states that the max data rates for 1.8V to 3.3V translation is 380 Mbps. Is that for an individual channel ?
- What is the Cpd(A) and Cpd(B) @108 MHz for our clock and 54 MHz for our data ?
