SN74LVC573A: SN74LVC573A Design Guide and Working Mechanism

Qiang Ren

Part Number: SN74LVC573A

Hello Team,

Currently my customer has some design guide and SN74LVC573A working mechanism questions, could you please help with it? Thanks!

Q1: What's the recommended connection of the signal pins, floating, pull up or pull down? Can you fill in the table as below:

Pin	Used	Un-used
LE
OE
D_IN		Pull down to GND
Q_output		Floating is ok

Q2: Is there timing sequencing requirement between the LE/D_IN/OE/VCC, I couldn't find it in the D/S. What may happen when the VCC comes after the LE/D_IN/OE?

Thanks!

over 1 year ago

0 Clemens Ladisch over 1 year ago

Guru 276380 points

1. Unused outputs can be left open. Unused inputs must not float. For unused D inputs, high or low does not matter; LE and /OE must be set according to what you want the device to do.

2. All inputs are overvoltage tolerant, so you can pull them up even before V_CC powers up. Due to the decoupling capacitors, the rise of V_CC will be so slow that there will be no timing problems.

0 Jack Campbell over 1 year ago

TI__Intellectual 1100 points

Hi Qiang,

In addition to what Clemens has said, please see this FAQ for more information on why CMOS inputs cannot be left floating.

0 Qiang Ren over 1 year ago in reply to Clemens Ladisch

TI__Intellectual 1475 points

Clemens and Jack,

Thanks for your reply. For further step, what's the theory/working mechanism that VCC can come after input signal?

We can use this example: customer requires that the device output stays low when the VCC just rises to high. And before Vcc rise to high, LE, D_in, OE are all low. What did the device do to keep the output to low when Vcc rise to high?

Thanks!

0 Clemens Ladisch over 1 year ago in reply to Qiang Ren

Guru 276380 points

See [FAQ] Can the input voltage (Vi) to my logic device be higher than the supply voltage (Vcc)?

To keep the outputs disabled during power up, you must keep /OE high.

0 Jack Campbell over 1 year ago in reply to Qiang Ren

TI__Intellectual 1100 points

Hi Qiang,

There can be no guarantee that the output will be high or low during/after power up until Vcc has reached the operating range and the appropriate inputs have been applied. Please see this [FAQ] What is the default output of a latched device? (Flip-Flop, latch, register) for more information on this.

If /OE is pulled high, even if Vcc to the device is not powered up, the device outputs will very likely be high impedance, though this cannot be guaranteed.

0 Qiang Ren over 1 year ago in reply to Jack Campbell

TI__Intellectual 1475 points

Jack,

There are two scenarios in this use case:

1. During device bring up(Vcc rising to high, but hasn't reach to operating level): According to your explain, the output status can't be determined before there is data input. We totally understand this feature and we will ignore the device output status in the system during device bring up.

2. The moment that Vcc has rise to operating range. Before this moment, LE/D_IN/OE# are all low. So what's the output status when the Vcc reached the operating range, at the same time the LE/D_IN/OE# still keeps low?

(a) If the output status is guaranteed to low, that meets customer's requirement and we just need to know the theory why the output is low;

(b) If the output status is un-determined before data comes, is there specific design or other device that can guarantee the output to low? You can ignore this case if (a) can meet customer requirement.

Thanks again for your support!

0 Clemens Ladisch over 1 year ago in reply to Qiang Ren

Guru 276380 points

The initial state is undefined; see [FAQ] What is the default output of a latched device? (Flip-Flop, latch, register)

To ensure that the output is low, LE must be pulsed high, or /OE must be pulled high with a pull-down resistor at the output.

0 Jack Campbell over 1 year ago in reply to Qiang Ren

TI__Intellectual 1100 points

Hi Qiang,

1. This is correct.

2(a). Low cannot be guaranteed.

2(b). Clemen's response is correct. In order to get low on the output at this moment either:

D_IN must be low and LE must be pulsed high to latch that valid data, or

/OE is high so that the device outputs are high impedance and a pull-down resistor is used on the outputs

Logic

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SN74LVC573A: SN74LVC573A Design Guide and Working Mechanism