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Hello all,
this is the circuit where i have a problem:
/cfs-file/__key/communityserver-discussions-components-files/151/CircuitDiagramQuestionTI.pdf
The clock is generated by the component: ECS-TXO-3225MV-122.8-TR This is fed into the SN74LVC74A. This is done so many times in total that the clock is reduced from 12.288 Mhz to 3.072 MHz and to 48 KHz after the fourth element. Soldered the prototype and then I noticed the following problem. It looks to me like the individual control signals are coupling into the supply voltage. If a load is addressed at 3.072 MHz, the supply voltage worsens. After now several days of testing, I was able to narrow down the source of the error to the SN74LVC74A. Also I have three different capacitors (22pF, 100nF, 1uF) instead of 100nF at the respective components placed. Unfortunately without success.
My question: Is the circuit for the SN74LVC74A correct? And additionally, how can I prevent the edge phenomenon "ringing" at the device. This seems to me also as a possible source of error.
Measurements:
Clock generated by the ECS-TX0-3225MV-122.8-TR
Output of the first SN74LVC
Output of the corresponding NB3N551DR2G
Power Supply 3V3 after i connect one probe to the output of the NB3N551DR2G and one probe to the Power supply
power Supply 3V3 when i only connect the probe to the power supply
power supply 3v3 when i have a load on 3MHz and 48Khz
Blue: Near the SN74LVC
Yellow: at the Power Supply
Oscilloscope: UNI-T UTD2052CEX
Probes: Sensepeek 2x SP100
Many thanks for your help in advance
The schematic looks correct. But are the capacitors near enough? Please show the board.
Each flip-flop has outputs that are strong enough to drive external loads. An integrated counter like the SN74LV4040A would generate less noise.
The capacitor placement look OK. Is this the smallest one?
But I don't see the power connections. Is this a four-layer board?
Thx Clemens. Do you mean the capacitor? I could go smaller in the next prototype. It is a two layer board. On the top and bottom side is a gnd polygon. 3V3 is routen with traces.
You mentioned three capacitor values, but I now see you put them on the same footprint.
Long 3.3 V traces might be a problem, but they also prevent the ringing from reaching other parts of the circuit.
Try the SN74LV4040A, and/or adding source termination resistors at the outputs. I would try to have planes for both power rails, but this is probably not achievable with two layers.
Yes, i tested with just one value. 100nF. But i thought maybe i need more. So i placed 3 sizes on top of each other. Output resistors at each SN74LVC74A? I didnt find anything in the datasheet
Source termination is method 4a on page 47 of the LVC Designer's Guide. (Your problem are not reflections, but a damping resistor might help a little.)
In the next iteration, i will place source termination on all four SN74LV's and i will try the circuit with the SN74LVC4040A. I think i can close this issue with resolved. Thank you Clemens.