• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 18 subscribers
  • Views 389 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN74LVC74A: Q output state after power up.

SYLVAIN BOURIOT
Intellectual 430 points

Part Number: SN74LVC7Hello,

Could I use an RC circuit on the /CLR pin?

I saw that in the datasheet that the input transition rise and fall time should be in 10ns/V. But I dont understand what it  will be the issue on this asynchronous pin.

Moreover, this "slow transition" on /CLR pin will only occurs at each powerup.

if  not, Do you have you a solution to be sure that Q output is at logic level "0" after power up.(I can't use  SN74HCS74).

 

Best Regards.

Sylvain

  • 0
    TI__Mastermind 45145 points

    Hey Sylvain,

    The biggest problem here would be the increased current which can be bad for strong LVC drivers, see this FAQ. I would recommend adding an external schmitt-trigger like the SN74LVC1G17 to handle the slow transition.