SN74HC11: Rise time synchronization

RAJAT RAJ

Part Number: SN74HC11
Other Parts Discussed in Thread: SN74HCS4075, SN74HCS11

Hi,

I am using a TI 3 Input AND (CD74HC11M96 ) and OR (CD4075BM96) gate in my setup, Below is a capture using Saleae logic analyzer. The inputs (GPIO-N1, GPIO-N2, and GPIO-N3) to both the AND and OR gates are low, but during a rising pulse, the AND gate goes high about 20 microseconds earlier than expected.

Also, by changing the Supply voltage (Vcc), within the operating voltage range for both the AND and OR gates, I've observed some unexpected toggling behavior, specifically occurring during the rising pulse..

Could anyone confirm this behavior or provide insights?

Thanks.

8 months ago

0 Clemens Ladisch 8 months ago

Guru 262480 points

I suspect that the input signals violate the input transition time limit. Please show an oscilloscope trace.

0 RAJAT RAJ 8 months ago in reply to Clemens Ladisch

Prodigy 10 points

Above images shows the scope capture. We can see some toggling on AND gate o/p during the rise pulse. The o/p of the OR gate is quite stable. Additionally, the voltage supply to these logic integrated circuits affects this toggling behavior. I'm hoping that these screenshots may help to clarify my question.

0 Clemens Ladisch 8 months ago in reply to RAJAT RAJ

Guru 262480 points

The rising edges indeed are much too slow. (See [FAQ] How does a slow or floating input affect a CMOS device?)

You need to use gates with Schmitt-trigger inputs, e.g., SN74HCS11/SN74HCS4075.

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SN74HC11: Rise time synchronization