CD4015B: Need to verify if my ouput is correct

Santhosh Kumar S

Part Number: CD4015B
Other Parts Discussed in Thread: CD4024B

Hello Everyone,

I'm using CD4015B Shift register in my design as shown in the attached image. Pin 9 is connected to 1MHz clock. For data input, we are giving inverted signal of the Q4.

We had expected a 250kHz pulses in each outputs Q1, Q2, Q3 & Q4. But now I'm getting 125kHz pulses in each outputs.

When I re-calculated it, it shows as 125kHz Only.

Can anyone please look at my design and help me on below my questions.

1. With 1MHz input, what should be the expected output frequency? is it 125kHz or 250kHz? please confirm.

2. If the output is 125kHz, is there any way to generate 250kHz frequency pulses with the same 1MHz input frequency?

REgards,

Santhosh

over 1 year ago

0 Clemens Ladisch over 1 year ago

Guru 317370 points

When powering up, the contents of the flip-flops are unspecified; see [FAQ] What is the default output of a latched device? (Flip-Flop, latch, register) So the output frequency could be between 125 kHz and 500 kHz.

To divide a clock signal down, use a counter/divider like the CD4024B.

0 Santhosh Kumar S over 1 year ago in reply to Clemens Ladisch

Prodigy 200 points

Thans for the answer.

When you say 'the output frequency could be between 125 kHz and 500 kHz'. Does it mean the output frequency value will be always varying between 125kHz & 500kHz?

But I'm measuring it in the oscilloscope, it is always 125kHz.

Regards,

Santhosh

0 Clemens Ladisch over 1 year ago in reply to Santhosh Kumar S

Guru 317370 points

When all four flip-flops power up with the same value (0000 or 1111), the output frequency is input/8.
When the two first flip-flops power up with the same value, and the other two with the inverse value (0011 or 1100 or 1001 or 0110), the output frequency is input/4.
When the four flip-flops power up with alternating values (0101 or 1010), the output frequency is input/2.

That all four flip-flops power up with the same value is likely, but not guaranteed.

0 Santhosh Kumar S over 1 year ago in reply to Clemens Ladisch

Prodigy 200 points

I agree that during the power up, as the contents of the flip-flops are unspecified initially, there will not be the values which i expect. But after few seconds or after some clock cycles, everything will be stabilized right? Because each output will be shifted and looped back to data inputs in each clock cycle.

So, I believe after few clock cycles, the frequency is guaranteed to 125kHz. Please correct me if I'm wrong.

0 Clemens Ladisch over 1 year ago in reply to Santhosh Kumar S

Guru 317370 points

The four bits are being inverted continuously; after eight clock cycles, they are in their initial state again.

0 Santhosh Kumar S over 1 year ago in reply to Clemens Ladisch

Prodigy 200 points

ok but I'm observing the output pulse from last 1 week. It is always 125kHz, I never saw any of the shift register outputs changing its state incorrectly in between.

+1 Clemens Ladisch over 1 year ago in reply to Santhosh Kumar S

Guru 317370 points

Because they happen to power up with the same value.

0 Santhosh Kumar S over 1 year ago in reply to Clemens Ladisch

Prodigy 200 points

Ok thanks for the answers

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CD4015B: Need to verify if my ouput is correct