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Original question:

LSF0102: Pull up resistor selection

LSF0102: Can I use a single R_pu and C pair connected to the EN pin for multiple translator devices

Randy Casciola
Prodigy 50 points
Part Number: LSF0102
Other Parts Discussed in Thread: LSF0002, TXS0102, LSF0204

Tool/software:

Hello,

I have a severely space constrained PCB where I'm using multiple LSF0102 devices (currently 10 of them). All translators will always be ON. Saving 9x 200K/0.1uF passives would be helpful. Can I connect the EN pin of all of my translators to a single 200K Pull up/0.1uF cap? If not all 10, can I do some number > 1? If that's possible, should I adjust the value of the 200K downward in some way to account for a greater total leakage current from VrefB to VrefA?

Thanks, Randy

  • 0
    Guru 278560 points

    You cannot share the biasing circuit.

    The LSF0002 does not require those passives and has a smaller package.
    The TXS0102 also integrates the pull-up resistors (but also has edge accelerators, which adds more restrictions).

  • 0 in reply to Clemens Ladisch
    Prodigy 50 points

    Thanks for the quick reply, Clemens! The LSF0002 was originally in the design, but is out of stock everywhere so I switched to the LSF0102. The LSF0204 has those parts integrated, so I'm looking at that one.

    Thanks again,
    Randy

  • 0 in reply to Randy Casciola
    TI__Mastermind 25701 points

    Hi Randy,

    LSF0204 also be used here with all devices' EN pin being referenced to single GPIO input signal. What is the intended application? Is this for I2C or GPIO translation? (If LSF0204 is used in series, note that the MCU will need to be able to sink in all the current through the FETs). 

    Feel free to provide block diagram of application for further clarification as needed.

     

    Regards,
    Jack

  • 0 in reply to Jack Guan
    Prodigy 50 points

    Hi Jack,

    The application is an interposer in a 25 year old design to replace an EOL FPGA. Everything is push-pull. The new FPGA is only 3V3 VDDIO, but the main board has a 5V CPU from NXP. We need to do some unidirectional 3V3<>5V, and some bidirectional 3V3<>5V. And it all has to fit (translation ICs and 3V3->5V boost) in the same footprint as the original FPGA (208pin PQFP). Hence the need to save space.

    Thanks,

    Randy

  • 0 in reply to Randy Casciola
    TI__Mastermind 25701 points

    Hey Randy,

    Thanks for providing the block diagram, customer may also see LSF0204 (4-ch. equivalent of LSF0102) with the integrated 200kohm bias resistor reducing space.

    Regards,

    Jack