SN74AVC4T245-Q1: Question about the requirement of input transition rise fall rate

Xiaochen Gao

Part Number: SN74AVC4T245-Q1

Tool/software:

Hi TI Team,

The datasheet specified a maximum rise or fall rate of 5ns/V.

I want to know does the input signal still need to meet this requirement in the case of OE being pulled high and the device being disabled?

In our current design, the input signal may not meet this rate requirement. We would like to confirm whether the risk caused by a slow signal rate can be avoided by disabling the device.

Thanks~

9 months ago

0 Xiaochen Gao 9 months ago

Prodigy 50 points

Additionally, I observed this oscillating waveform at the input and output, and I want to know why a slow input signal would cause such oscillations?

0 Joshua Salinas 9 months ago in reply to Xiaochen Gao

TI__Mastermind 23600 points

Hello Xiaochen,

Please see this FAQ for additional information on why slow inputs should be avoided.

[FAQ] How does a slow or floating input affect a CMOS device?

Regards,

Josh

0 lelian cao 9 months ago in reply to Joshua Salinas

Prodigy 160 points

Hi Joshua:

Could you explain us how this oscillation happens? Is it related to the characteristic of CMOS, or the logic inside the chip?

We checked this post already, but still do not understand the theory behind the output oscillation near threshold value.

Thanks

0 Clemens Ladisch 9 months ago in reply to lelian cao

Guru 317370 points

See section 2 of the application report linked to by the FAQ.

Logic

Logic forum

SN74AVC4T245-Q1: Question about the requirement of input transition rise fall rate