Tool/software:
Hi,
We have the question for the design of CD74HC73M96, the J and K is high that the outputs logic is toggle(refere to the below truth table);
And now, we use the hardware design to set the J and K to high and the power supply is normal, and ther are no triggering signal,
we want to know the Q and /Q initial outputs logic states, it is the fixed or random state? thanks.
