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TPLD-ICS: Erratic latch behavior

Part Number: TPLD-ICS

Tool/software:

Hello,

As I had issues with counters (see the other post), I decided to fix the problem by resynchronizing the reset signal using 2 DFF on the same clock than the counter.

It worked out for the counter output issue (bug ?).

However, now the latch does not seem to work or I don't understand how it supposed to work.

I have done the following:

However, I am observing the following:

As you can see the counter does output a pulse, however that pulse going high does not generate a high level, i.e., the expected latch.

I am doing something wrong or is there an issue ?

Clément