TPLD1202: WD configuration issue

Clément Letonnelier

Expert 2816 points

Part Number: TPLD1202

Tool/software:

Hi,

I had time to get my hands on the the WD configuration.

I can't get the WD to work as intended...

I have the following design:

The delay is used to block the watchdog for a duration after reset.

I have the following WD block configuration:

And the WD refresh simulation parameters are the following:

I am observing the following curve:

As you can see I am toggling the refresh input at a 10µs rate and I have configured the watchdog for 100 osc1/2 cycles so I would not expect the wd to trigger a fault, but it does.

Any ideas ?

Clément

3 months ago

0 Malcolm Lyn 3 months ago

TI__Mastermind 26140 points

Hi Clement,

Could you share the syscfg file with me please?

Best,

Malcolm

0 Clément Letonnelier 3 months ago in reply to Malcolm Lyn

Expert 2816 points

Hi Malcolm, Here you go:

2063.pre-design.zip

0 Malcolm Lyn 3 months ago in reply to Clément Letonnelier

TI__Mastermind 26140 points

Hi Clement,

The watch dog timer appears not to work in simulation (always triggers regardless of what happens on the input). The real device does not work like this. It seems there was an issue in how the verilog model translated to SPICE.

Best,

Malcolm

0 Malcolm Lyn 3 months ago in reply to Clément Letonnelier

TI__Mastermind 26140 points

Clement,

If you are interested, I have developed a fix for the watchdog timer. Due to how we release this fix won't be in the software for another few months as I said in another thread, but if you're willing to go into a directory and change a file that would let you properly simulate the WDT before you can test on hardware.

Let me know if you'd like this and I will provide instructions on how to make that change.

Best,

Malcolm

0 Clément Letonnelier 3 months ago in reply to Malcolm Lyn

Expert 2816 points

Malcom,

Yes definitely please, otherwise it would lead to a no-go for the usage of the part and we have a decision point in early September.

Clément

+1 Malcolm Lyn 3 months ago in reply to Clément Letonnelier

TI__Mastermind 26140 points

Hi Clement,

I have attached the file that is responsible for the WDT's simulation behavior. The issue was that some internal delays were not generated correctly, it was a one line change. You can see your file behaves as we would expect it to now:

To implement this change, navigate to where you have installed whatever version of interconnect studio you are using and replace the wdt.mod file with the one I've attached to this response. For me, that directory is:

C:\ti\interconnectstudio_1.5.0\product\source\ti\tpld\.meta\templates\subcircuits

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/151/wdt.mod

Best,

Malcolm

0 Clément Letonnelier 3 months ago in reply to Malcolm Lyn

Expert 2816 points

It solved it thanks.

Clément

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TPLD1202: WD configuration issue