Other Parts Discussed in Thread: SN74AUC17
Tool/software:
Hi TI team,
Use case: I’m translating 1.8 V → 3.3 V single-ended signals. I need 16 channels total, so I’m planning on using two TXV0108RGYR devices. I only need the A->B direction. I'm attempting to meet timing for a customized protocol.
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VCCA = 1.8 V, VCCB = 3.3 V
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Load is light (few pF per line)
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Priority is tight skew and low propagation delay
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I understand the datasheet shows A→B tpd ≈ 1.1–3.1 ns and in-device channel-to-channel skew ≈ ±330–400 ps.
Q1) Device-to-device matching / inter-chip skew (TXV0108)
When I split 16 lines across two TXV0108s, is there any published or characterized data on device-to-device propagation matching? The datasheet gives in-device skew, but I don’t see a spec for inter-device skew. Practically speaking:
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Should I budget the full tpd min→max spread (~2 ns) as potential inter-chip skew, or is there typical characterization guidance that’s tighter?
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Any recommendations to minimize inter-device skew (e.g., mapping each timing group entirely within one IC, rail decoupling/layout tips, lot matching, etc.)?
Q2) Running SN74AUC17 at 3.3 V
I’m also evaluating SN74AUC17 (Schmitt-trigger buffer). It looks optimized around 0.8–2.7 V, and the absolute max VCC is 3.6 V. What are the consequences of operating it at 3.3 V (DC supply), specifically:
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Is this outside the recommended operating conditions (and thus parameters not guaranteed), or is there any characterization at 3.3 V?
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What degradations should I expect (tpd, output drive, VOL/VOH, ICC, jitter), and are there reliability concerns at 3.3 V even though it’s below abs max?
Thanks in advance for any guidance, app notes, or characterization data you can share!
If there are other buffers or level shifters that work better for my application please let me know.
