SN74AUC1G08: skew

keith leisses

Part Number: SN74AUC1G08

I am looking for the package to package skew information for this part. In my case the parts will be at the same temperature and supply settings. Planning on 2.5V. Really just need a buffer and the AND is the closest thing I could find. Need the prop delay as I am passing 200MHz so the other families are too slow.

In case there is a better solution: really need to go from LVDS to 2 single ended signals 1:2 and 2 in parallel so 2x 1:2 LVDS / LVTTL [or similar] would be ideal. Barring that I am using a '28 to receive the two LVDS differential pairs and converting to single ended then the AND gates to buffer and keep from having stubs with the two end points for each. Leading to my skew question.

1 month ago

0 Malcolm Lyn 1 month ago

TI__Mastermind 33195 points

Hi Keith,

We don't explicitly spec skew for any of our devices. There are some translation devices that spec channel-to-channel skew on the same package, but none that specify package-to-package skew. For devices that do not explicitly spec channel-to-channel skew, we guarantee that skew will be <1ns typical between any two channels on the same package. We make no guarantees for package-to-package skew, although we would expect the same <1ns typical for two devices from the same batch.

(+) [FAQ] What is the difference in timing between gates in the same device? How much skew is expected within a given logic device? What is the part-to-part skew? - Logic forum - Logic - TI E2E support forums

Best,

Malcolm

0 Malcolm Lyn 1 month ago in reply to Malcolm Lyn

TI__Mastermind 33195 points

I'm not a clock buffer expert, but it looks like this part might meet your requirements and guarantees skew if you're ok with the added complexity:

LMK00804B Low Skew, 1-to-4 Multiplexed Differential/LVCMOS-to-LVCMOS/TTL Fanout Buffer datasheet (Rev. A)