Hi, I'm a student of Computer Engineering at the University of Sao Paulo (Brazil) and one of our disciplines involved this exercise where we should model some of the components described on the Texas Instruments Data Book (http://www.ti.com/lit/sl/scyd013b/scyd013b.pdf) in VHDL. While working on this project, I noticed something strange at the diagram of the 16-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER (page 300 of the DataBook). The AND gates directly in front of inputs E9 and E11 receive the same "data select" signals. According to the function table shown on the next page, the AND gate associated to the E11 input should be receiving the signals A, B, ~C and D instead of A, ~B, ~C and D. Could anyone confirm if this is correct?
