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SN74LVC1G123: pulse transition timing of INPUT pins

Shinichi Inoue
Guru 21676 points
Part Number: SN74LVC1G123

Dear Specialists,

My customer is considering SN74LVC1G123 and has a question.

Could you please advise?

---questions---

about INPUT pins (CLR, A and B) 

(1)Is it possible to transit when Rext/Cext is discharging?

(2)Is there any limitation of timing?

(3)At this time does Q output remain H?

(4)At the point of Table 1. Function Table, it may be possible to use.

Is it correct?

Could you please see attached file, it is illustrated in detail.

I appreciate your great help.

Best regards,

Shinichi

 short transition after first transition.pptx

  • 0
    TI__Guru 62120 points
    Shinichi san ,

    wanted to clarify if transition means high to low or low to high ? Since this is retriggerable , you can have input to retrigger the multivibrator to keep the outputs high.
    While Cext is fully charged , the output voltage is low and Cext discharges rapidly during trigger event (happens very quick) and starts charging back up.At this time, the output is high until it reaches the set threshold internal to device.
    The inputs transition needs to be outside of the retrigger time , otherwise , it will be ignored.
    with overiding CLR input, the Cext is instantly charged to Vcc ,so the output goes low.

    Please go through the app note about the sn74LVC1g123 operation here : www.ti.com/.../slva720.pdf .
  • 0 in reply to ShreyasRao
    Guru 21676 points
    Dear Shreyas

    Thank you for your reply.

    I understand that
    SN74LVC1G123 is retriggerable device, it can continue to output "H".
    and if input transition is in the trr, it is ignored.

    I am going to send your answer to the customer.

    If he has additional question, I'll talk with you.

    I appreciate your great help.

    Best regards,
    Shinichi
  • 0 in reply to Shinichi Inoue
    Guru 21676 points
    Dear Shreyas

    I'm sorry for sending many times.

    The customer has additional question, could you please advise?

    (1)When input transition is in the trr, it is ignored.
    At this time output holds the previous state, H to H or L to L.
    Is it right?

    (2)Also does device have any possibility to damage when input transition is in the trr?
    The pulse width is between 100ns and 200ns

    I appreciate your great help.

    Best regards,
    Shinichi
  • 0 in reply to Shinichi Inoue
    TI__Guru 62120 points
    Hi Shinichi san ,

    With retriggerable Multi-vibrator , you can trigger the device in between the pulse width and the output continues to remain high.
    with nonretriggerable multi-vibrator , the device ignores a trigger event within the pulse width of device.
  • 0 in reply to ShreyasRao
    Guru 21676 points

    Dear Shreyas

    Thank you for your reply.

    I explain customer's situation.

    Due to the long term changing of Cext capacitance( 22u to 18u) and ESR(5ohm to 200lhm), pulse width has changed.

    The pulse width became quite shorter than initial.

    In this case, the best measure is changing the capacitor, but the end user is not accept.

    For expanding pulse width, they are thinking of using input pin.

    You meitioned before, it is gnored between trr, but  they keep inputting pulse, because they can't know how long is the pulse width.

    They would like to know whether or not the device is damaged when there is transition of input pin within trr.

    I appreciate your great help and cooperation.

    Best regards,

    Shinichi

  • 0 in reply to Shinichi Inoue
    TI__Guru 62120 points
    Shinichi san ,

    There shouldnt be any damage when there is input transition on the pins. Within the trr , the transition would be ignored.
    Outside the minimum retrigger time, the pulse width remains high when there is input trigger.
  • 0 in reply to ShreyasRao
    Guru 21676 points

    Dear Shreyas

    Thank you for your reply and helpful information.

    I'll send your answer to the customer and consider.

    I appreciate your great help and cooperation.

    Best regards,

    Shinichi