Original question:
The resistors values used to set the Fmax and Fmin does not produce the same frequency band for different ICs.Is there an way to get the frequency band from fmay to fmin with always the same frequecies with different ICs. My fmin= 35.4kHz and fmax is = 36,6kHz , a bang of 1,2kHz.I am using 680kOhms and 36kOhms resistors with C = 820pF.
I am sending you the diagram of the oscilloscope waveforms. When I apply Signal at the Ref(pin 14) and the comparator pins(pin 3) I get Signals on the PD1 (pin2) and PCP OUT (pin1) but I do not get any Signal on the PD2 PC2 OUT (Pin 13). I have changed many ICs but it does not work.
Yellow is Comparator, Blue SIG_IN (pin 14) and Red is PD1(Pin 2).
Yellow is Comparator, Blue SIG_IN (pin 14) and Red is PCP_OUT(Pin 1).
Yellow is Comparator, Blue SIG_IN (pin 14) and Red is PD II(Pin 13).
Thanks for the detailed response - this is very helpful to me.
PC2 can be problematic in some systems. Here's the logical structure:
I know the logic is a little hard to follow on this -- I cleaned up everything except PC2 here to try to help. Note that the output can drive either HIGH, LOW, or not at all (Hi-Z). This is specifically controlled by the rising edges of the incoming signals. The problem occurs when you get 2 or more rising edges on one signal while the other signal only has only 1 rising edge. This will cause the logic to get, for lack of a better term, out of cycle. Usually, this is how the system would work:
(1) If SIG_IN rising edge leads COMP_IN rising edge, then the pFET at the output turns ON and the output is driven HIGH -- until the COMP_IN rising edge is seen and the output switches back to High-Impedance mode.
(2) If COMP_IN rising edge leads SIG_IN rising edge, then the nFET at the output turns ON and the output is driven LOW -- until the SIG_IN rising edge is seen and the output switches back to High-Impedance mode.
(3) If the two signals are in phase, both signals clock at the same time and both DFF's get reset at the same time, keeping the output in the High-Impedance state.
As long as the inputs remain consistent, there's no issue. The output voltage will be increased when COMP_IN leads SIG_IN and decreased in the opposite case.
A problem can occur if two edges come in on one input, in which case the phase difference will be read as the opposite of what it actually is. It's possible for the device to become "confused" and end up forcing the output the wrong direction, creating a positive feedback loop that just rails out the output.
The best method I have seen to prevent this issue is to use the PC1 output instead, or to force the device into the other mode of operation by putting multiple triggers on the opposite input to the one that is 'stuck.'
I put together a state machine diagram to help explain. Hopefully it doesn't just add confusion.
So, in this diagram, you can see that's it's possible to be in S1, then get a double trigger on SIG_IN and end up in S3 when you really _want_ to be in S2. This will result in a reversal of the desired output (S2 to S3 oscillation instead of S1 to S2 oscillation), and the output gets 'stuck' at the rail.
I dont think it is the Problem which you are mentioning. I have connected a pull up and a pull down resistors on the PD2 output (Pin13). Now you can see that it is working but with an Offset of 2.5V which brings the VCO at the centre frequency and then a small negative pulse cannot bring it down to the Zero Phase. There is somthing wrong the IC circuit. There seems to be no flip flop state Problem. With pullp resistors I cannot make the Phase Zero but brings it slightly below the centre frequency. Is there any solution that the PD2 works without Pullup and pull down resitsors in standard way.
Blue is Comparator, Yellow is Reference and the red is the PD2 Output after pull up and pull down with 2k resistors.
Hi Tahir,
In my opinion, your latest scope shot and explanation continues to agree with my description of the issue.
This scope shot shows that the device is driving the output LOW between (1) and (2), and the output is in high-impedance between (2) and (3), allowing the resistor divider to take over and hold the line at ~Vcc/2. This indicates that the device is operating in state S1 (from my earlier diagram) between (1) and (2), and S2 between (2) and (3).
My assumption is that you need the PC2 output to drive HIGH (in S3) between 2 and 3 to fix the phase imbalance, but the device is stuck oscillating between S1 and S2, when it should be oscillating between S2 and S3 to fix the imbalance.
Yes, the logic diagram in the datasheet shows exactly what you have in the scope shot -- ie the part is doing exactly what it's supposed to be doing under this circumstance.
Perhaps I have misunderstood the issue?
Here's a markup of the datasheet to match my state diagram:
At (1) the SIG_IN rising edge switches PC2 into S1, switching on the pFET at the output. At (2) the rising edge at COMP_IN switches the device into S2, putting the output in Hi-Z mode. When both edges are seen at the same time (3), the device remains in S2. At (4) when the COMP_IN signal has a rising edge first, the device switches from S2 to S1, forcing the output low, and then it returns to S2 when SIG_IN goes high again.
This is all the correct operation of the device, and matches what you're showing.
