SN74AUP2G00: Reset dominant SR latch

Hi Pradeep,

The first result for this question on google has a pretty decent answer: https://electronics.stackexchange.com/questions/64831/given-a-gated-sr-latch-how-do-i-make-it-a-set-dominant-gated-sr-latch

I think you could also do this instead, depending on your exact definition of "reset dominant":

This just adds a little delay in the reset feedback loop, so if S\ and R\ are asserted at the same time, then released at the same time, the output should settle on Q = L and Q\ = H.  I think it's possible that this could also turn into an oscillator under the right conditions (I haven't been able to get it to happen in simulation though); the more complex solution linked above is probably the better bet.

Here's a simulation of the above circuit:

As long as the buffer is faster than the NAND gates, then it should prevent oscillation from occurring. You can see above that the Q\ output tries to switch low, but it isn't fast enough to fully switch, and the output returns high. Lighter loads produce even less of a glitch in the output.

Hey Pradeep,
Yes, to all of the above. The first circuit does what you think it should, and the following two are correct conversions to NAND logic.

Is there a reason you're wanting to only use NAND gates? The solution I showed would be smaller and simpler with less total delay. You could do this whole thing with just a single SN74HC00 (or any of the '00 quad NAND gate devices), but they would be much larger and use more power than the SN74AUP2G00 + SN74AUP2G17 solution, or even the 2x SN74AUP2G00 solution.