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Original question:

SN54F74: Need IBIS model

SN74F74: IBIS model issues

Scott Asher
Intellectual 500 points
Part Number: SN74F74


Hello,

I'm having some problems with the IBIS model for the SN74F74 I was hoping TI could help to resolve. The model I downloaded from the TI website is sn74f74.ibs.

First I simulated an output rising edge at typical case setting. Then I simulated an output rising edge at Slow-Weak setting. Then I compared the two waveforms and found that they are almost exactly the same which does not seem correct. I would have expected the Slow-weak rising edge to be much slower than the rising edge for typical, and not an almost exact copy as the simulations shows. I also found the same problem when comparing typical to Fast-Strong rising edges. The Fast-strong rising edge was almost exactly the same as the Typical rising edge. Not faster as one would expect the Fast-Strong edge to be. Also found for falling edge simulations that Typical and Fast-Strong falling edges were almost exacting the same. Again, the Fast-strong falling edge was not faster than Typical falling edge as one would expect. 

Also, when I run the file through an IBIS checker program, I get the following caution messages:

CAUTION - [Ramp] dV ( 1.910V) not within 5.00% of I-V table dV ( 2.039V) calculation: Model f74_OUT: Process: TYP: (Rising)
CAUTION - [Ramp] dV ( 1.570V) not within 5.00% of I-V table dV ( 1.671V) calculation: Model f74_OUT: Process: MIN: (Rising)
CAUTION - [Ramp] dV ( 1.510V) not within 5.00% of I-V table dV ( 2.555V) calculation: Model f74_OUT: Process: MIN: (Falling)

Errors : 0
Cautions: 3

Can TI explain what is going on here and resolve these issues with the model? Otherwise we are not sure we can trust the accuracy of this model.

Thanks,

Scott

  • 0
    TI__Genius 9775 points
    Hi Scott,

    FYI, one of our team will take a look at this.

    Herman
  • 0
    TI__Mastermind 20460 points

    Hi Scott,

    In looking at this model, I see in the [Notes] that this model was extracted from lab mesurements. That's about as good as it gets. Most models are based on simulation as it can be difficult to get a clean bench setup that doesn't introduce ground bounce and noise effects into the VT data. You'll see in the falling data a bit of overshoot and ringing. That's definitely a bench artifact and not due to the device architecture.

    As a result of this being a measurement based model, only nominal silicon would have been available for the model. So the corner conditions represent temp and voltage variations only.

    You certainly see the voltage impact on how high the output goes.

    The temp variation is limited because the temp range is 0 to 70C. CMOS will be pretty stable across that temp range. It needs to get above 100C before the CMOS gets weak.

    The only Caution that looks worrisome is the MIN:(Falling). It looks like the EDA tool is only comparing against the Ramp to VDD, and not looking at the RAMP to GND. RAMP to GND would have a dV is roughly 1.6V.

    I hope this explanation helps.

    Regards,

    David Larkin

    CAE-Modeling