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SN74LVC14A: insert a capacitor on the pin

user1367489
Prodigy 110 points

Part Number: SN74LVC14A

Does case1, case2 circuit have problems on the input/output pin of SN74LVC14A?
We have concern, that is the repeat of charge to and discharge from the C1 or C2 capacitor may damage to input/output pin of SN74LVC14A and then break the pin.
Could you tell what we should things for consideration except slope on input/output pin?
Should we only consider Iik and Iok spec. of SN74LVC14A?
If some consideration, could you let us know?

Case1, Case2 circuits are in the attached file.

Question_SN74LVC14A_Oct21_2019.pdf
 

  • 0
    Guru 326790 points

    In case 1, charging is slow because R1 limits the current. When discharging, current flows only through C1 and the transistor. The only problem that could happen is if the trace impedance is so high that you get strong ringing at the inverter's input. Do you have long traces, connectors, or cables?

    In case 2, both the charge and the discharge current are limited by R2.

  • 0 in reply to Clemens Ladisch
    TI__Mastermind 48245 points

    Hi,

    There isn't really concerns with the circuit itself, but as Clemens has stated there is possibility of damage if there is a large overshoot. The chances for such large overshoots are pretty low due to the cap at the input, but this will also be affected by the layout/PCB so make sure not to have excessively long traces that can increase the inductance on the line.

  • 0 in reply to Dylan Hubbard
    Prodigy 110 points

    Thank you for answer and advice.

    In case 2, I have two questions as below.

    a) I think the right-side SN74LVC14A input pin is dameged by discharging from C2.

        How do you think?

    b) Could you tell me a way to decide the value of R2 and C2? 

  • 0 in reply to user1367489
    TI__Mastermind 48245 points

    Hi,

    A) No, if you are concerned about the slow transition, this won't be a problem as this device has a schmitt-trigger input.

    B) I don't know how to determine this, I don't know what you are trying to achieve with this circuit.

  • 0 in reply to Dylan Hubbard
    Prodigy 110 points

    Hello,

    Thank you for your response rapidly.

    A) 　I understand.

    B)　The reason I'd like to know is for reducing overshoot or undershoot voltage with R,C.    

           However I think if a large value of capacitance(ex.C2) are placed between the driver and reciver with no the register(ex.R2), the driver(output) pin and reciever(input) pin may be damaged, since current flowing and  voltage applying from the capacitor(ex.C2) damage to protect diodes on the driver/reciever-pin.

         I think my expecting answer is related to the Iik and Iok spacifiction of the device.

         I 'm asking with using SN74LVC14A in case2 circuit, but I want to know the way in case of using other std logic family.

         Could you provide your opinion? 

  • 0 in reply to user1367489
    TI__Mastermind 48245 points

    Hi,

    R2 needs to be there to protect the output driver since there will be nothing limiting the current into the cap. That value should be set with the IOH/IOL specs of the datasheet. This way at t=0 when the cap is a short the current shouldnt exceed the datasheet spec. As for the input side, the filter should eliminate the ringing right? If not, then the only time current will flow through diodes is when the signal goes .5 V beyond VCC or GND (just GND for this device). Again with that cap there I don't see this being an issue. If it is, another resistor will need to be placed at the following input to limit the current to something under the IIK value in the datasheet.

  • 0 in reply to Dylan Hubbard
    Prodigy 110 points

    Hello,

    I cleared my concern with your clarification.

    Thank you veru much.

    I have one more question.

    ---

    What max loads(capacitance) can the output pin of the device have? 

    Is the max loads in the datasheet of the device?

    If yes, plese let me know in case of SN74LVC14A. 

  • 0 in reply to user1367489
    TI__Mastermind 48245 points

    Hi,

    We don't spec max capacitive loads for our device, but we typically recommend keeping it under 70 pF if possible. However, it can be higher as long as the current spec isn't being exceeded and your system doesn't have any issues with the output slew rate being slowed.