SN74LVC1G175: Detail Spec for the rising edge

Wu JW

Part Number: SN74LVC1G175
Other Parts Discussed in Thread: TLV7031

Hi,

My customer want to know the detail spec for the rising edge for the SN74LVC1G175. We can't find the spec in the datasheet. Could you give some suggestions for this?

1. How about the detail spec for IC to judge the rising edage for the CLK pin? The threshold V? The rising time(the min value and the max value)?

2. Customer want to detect the rising edge for their system application. In a 5V supply system, they want to use a pulse as 100ms slow rising time with 3.2V high level at the CLK pin, can it make the Q flip to the high level?

3. If not, do you have any suggestion to detect the rising edge for the CLK pin?

over 4 years ago

0 Clemens Ladisch over 4 years ago

Guru 277220 points

This circuit might not work because the device can start up with a high output; see [FAQ] What is the default output of a latched device? (Flip-Flop, latch, register).

CMOS inputs have a voltage threshold, but it can be anywhere between V_IL and V_IH, so 3.2 V is too low. Furthermore, a rise time of 100 ms is much too slow; see [FAQ] How does a slow or floating input affect a CMOS device?

It would be possible to add a Schmitt-trigger buffer in front of the CLK input if a 3.3 V supply is available and if the threshold for the 3.2 V signal does not need to be tightly controlled. Otherwise, you have use a comparator (e.g., TLV7031).

0 Chad Crosby over 4 years ago

TI__Expert 6680 points

Hi JW,

Clemens is correct. Unfortunately for this device, the clock signal rises too slowly and does not rise to a high enough level, which might cause in unwanted results in operation of the device. To address your concerns specifically:

1. Sections 6.6 & 6.7 of the datasheet give details about the timing of the CLK signal, and section 6.3 (V_IH) gives the spec for threshold V)

2. No, this clock signal will not be enough to toggle the Q output.

3. See Clemens's reply.

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SN74LVC1G175: Detail Spec for the rising edge