TXS0108E: DC bias

I'd guess two devices are pulling high and low at the same time.

In which direction does the current flow, i.e., what is the voltage drop over the TXS?

Hi Clemens,

Thanks for responding.

Current flows from the 3.3 V to 1.8 V. 

I am not sure about the voltage drop you are referring to.?

I would like to also mention that the TCK signal was translated properly from 3.3 V to 1.8 V and is running at 6 MHz. We are not able to understand why this is happening on one signal. If the part would have been faulty or if the drive strength of the jtag cable is not good enough I wouldn't have expected the TCK to translate properly.

Thanks,

 Ramu

I mean the voltage drop over the switch, e.g., the voltage between the A5 and B5 pins. (When the switch is closed, the connection behaves like a resistor with about 250 Ω).

Please show the schematic.

H,

Sure we will do that.

Attached below is the schematic

This schematic does not show what is connected to the TMS signals.

The JTAG_TMS signal on the 3.3 V side is going to the FPGA and the translator as shown below and the 1.8 V side of the translator is going to the other FPGA. 

Hi,

Are pins 15, 13, and 12 left floating on U102?

Thanks!

Chad Crosby

Hi Chad,

Yes they are left floating. Not connected to anything.

Is there a issue with that..?

Hey Ramu,

Thanks for the schematic and details. This looks to be a pretty straight forward connection. My current expectations are similar to Clemens, it may be that both devices are driving at the same time. Were you able to perform the measurement across the switch that he requested? This data point will help.

Hi Dylan,

Sure we will try that experiment and update you. The jtag_TMS is an input pin. I am not sure why the both devices will be driving it at the same time. We use a standard JTAG cable from xilinx to initiate the boundry scan. 

Hi All,

We have four translators on our board and for every translator we noticed that we have a problem with A1 and B1 pins ( Pin 1 and Pin 19).

When we removed the connection on A1 and B1 pins and connected it to the other pins which we were not using in this case B8 and A8 we see that it is working fine. So from this experiment we can concluded that the FPGA's were not driving the pins A1 and B1. We think that it is something to do with the Translator TXS0108E.

We want to understand what is the difference between A1 and B1 pins compared to all other pins. Internally are these two pins connected differently. It was surprising for us to see this happen on 4 of the translators we are using. 

Thanks,

 Ramu

Hey Ramu,

There are no differences in the data channels.

Thank you for the response, as you can see above the schematic is pretty straight forward, so we are not able to understand what might have caused this issue.

Any idea..??

Hey Ramu,

Were you able to do any current measurements? There is something that is pulling the line high other than the internal 10 kohm resistor ( this should be easily over driven). I would expect to see high currents going through the TXS device if this was the case. Measuring across the A and B side would show a significant voltage shift. This is the only thing I could think of with this simple connection ( Even if there was device damage causing this, I'd expect to see some high currents.