SN74LVC74A: CLK input transition time

ReedKacz

Part Number: SN74LVC74A
Other Parts Discussed in Thread: SN74HCS74

Hi Logic Experts,

My customer is using the SN74LVC74A in two different applications on the same design. I have a few questions.

1. The datasheet specs the MAX transition rise/fall rate at 10ns/V. What happens if you exceed this rise/fall rate for the CLK input? My customer has a 5ns rise time for their 3.3V CLK input (1.5ns/V rate).

2. Does the device care if the rise and fall edges are very different timing? The CLK falling edge is 5ns in one use case but the rise edge is very slow at ~70us.

Thanks!!
Reed

over 5 years ago

0 Clemens Ladisch over 5 years ago

Guru 316600 points

The rising edge is much too slow, and might damage the device. See [FAQ] How does a slow or floating input affect a CMOS device?

Add a Schmitt-trigger buffer, or use the SN74HCS74 instead.

0 ReedKacz over 5 years ago in reply to Clemens Ladisch

TI__Expert 3462 points

Hi Clemens,

Thanks for the response. That is a helpful reference showing that the input stage will be stressed for the slow edge.

What about the speed of 5ns rise time, is this going to be too fast?

-Reed

0 Clemens Ladisch over 5 years ago in reply to ReedKacz

Guru 316600 points

There is no minimum rise/fall time.

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SN74LVC74A: CLK input transition time