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Original question:

SN74LVC1G123: Glitch-Free Power-Up Reset on Outputs

SN74LVC1G123: Glitch-Free Power-Up Reset on Outputs -->

Sven Markovits Hoopii
Prodigy 20 points
Part Number: SN74LVC1G123

In addition to the forum article "SN74LVC1G123: Glitch-Free Power-Up Reset on Outputs"
e2e.ti.com/.../947998

we get an undesired output pulse at power-up. 

Our design holds  !A and B low. !CLR and VCC come up together. In this case no output pulse should be generated. 
We have a VCC rise time (10% to 90%) of ~ 0,2ms (25V/s). 
Now, sometimes the output generates an pulse when VCC is rising. !A and B is holding low. 

When I increase the rise time for example to 350µs there is no undesired output pulse generation. 

Is there a defined minimum ramp time for VCC-rise at power up for Glitch-Free Power-Up Reset?

Thanks!

  • 0
    TI__Guru* 96711 points

    Hello, and welcome to the forums!

    There isn't a defined power on ramp rate, but there probably should be.

    The power-on reset circuit is essentially just an internal RC circuit that provides a defined state at startup. If the power supply is ramped very slowly, the circuit is effectively bypassed.

    Since this wasn't characterized when the device was initially produced, I don't have any data to refer to for providing a limit on the supply ramp rate.

    Looking into devices with similar power-up based circuitry, the ramp rate is typically limited to 200 µs/V to guarantee operation. This is probably a good value to use.

  • 0 in reply to Emrys Maier
    Prodigy 20 points

    Thanks Emrys for the prompt support.