CD4013B: CD4013B input and output issue

Sherry Liang

Part Number: CD4013B
Other Parts Discussed in Thread: SN74LVC2G74

Dear team,

Recently my customer wants to use our CD4013B to replace NLV1403BDR2G, and they have two questions about our device.

1. Before they use NLV1403BDR2G, when this device powers down, and SET pin is high, Q pin output will be high because every pin's diode as below.

Does our CD4013B have the same phenomenon? When CD4013B powers off, what is the Q pin output under SET pin=H state?

2. When NLV1403BDR2G powers up, Q pin will output a high level even though no input as below. Does our CD4013B have the same phenomenon?

Thanks & Best Regards,

Sherry

over 4 years ago

0 Clemens Ladisch over 4 years ago

Guru 316640 points

1. All CD4000 devices have these ESD protection diodes. See [FAQ] Can the input voltage (Vi) to my logic device be higher than the supply voltage (Vcc)? and [FAQ] Is the reliability of a logic device affected by applying an input voltage larger than the supply (VCC)?

Consider using a device with overvoltage-tolerant inputs, like the SN74LVC2G74.

2. The initial output state is undefined, and might be high. See [FAQ] What is the default output of a latched device? (Flip-Flop, latch, register)

0 Emrys Maier over 4 years ago

TI__Guru* 97046 points

Hi Sherry,

The assertion that "Q pin output will be high because every pin's diode as below" is incorrect. The positive clamp diodes won't have an impact on the output state of the internal latch circuits.

The startup state of a latched device is unknown -- the ON datasheet makes no assertion that they guarantee a startup state of HIGH at the output -- or at least none I could find.

The CD4013B also has positive clamp diodes and also does not guarantee a specific output state on startup. The SET and RESET pins can be used to force the outputs to a desired state at startup, or data can be clocked through.

There's more info on latched circuits here: [FAQ] What is the default output of a latched device? (Flip-Flop, latch, register)

0 Sherry Liang over 4 years ago in reply to Emrys Maier

TI__Genius 10255 points

Hi Maier,

Thanks for your reply!

About the first question, when powers off, Q pin is always 0 no matter what the input is, right?

Thanks & Best Regards,

Sherry

0 Clemens Ladisch over 4 years ago in reply to Sherry Liang

Guru 316640 points

When the power is off, the output pins do not actively drive any value.

If you see a high voltage at an output, this is probably because the diode current from an input pin is flowing into V_CC and has powered up the device.

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CD4013B: CD4013B input and output issue