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recommended PLL IC

FRANK1
Expert 8695 points
Other Parts Discussed in Thread: SN74LV4046A, LMK5C33216

Hi Sir,

A customer is looking for PLL IC which can take input of 288kbps(line rate) and gives locked output of 256kbps for our internal customized equipment.

He is also looking for multi channel Phase-Locked Loop with VCO.

He is having eight different clock inputs and eight different locked (VCO out) clock output for our customized communication board.

so He needs to use 8 IC's SN74LV4046AD which we want to minimize it.

So kindly suggest the required IC which can meet our requirement of multi channel Phase-Locked Loop with VCO.

Actually he found ine IC whch can meet one purpose but im looking for multichannel.
i.e. Multichannel PLL IC

is there any suggestion?

Thanks.

Regards,

  • 0
    TI__Mastermind 34270 points

    Hello FRANK1,

    We definitely don't have any device with eight clock inputs, eight separate PLLs, and which can operate at 288kHz input on the same device. The low-frequency PLLs like SN74LV4046A are all single-PLL circuits. Higher PLL count devices do exist, but typically only take one reference input and generate multiple clock outputs from them. Most of our multi-PLL devices are intended for high-frequency operation (>10MHz) or are significantly overfeatured for the customer requirement.

    256kbps is low-frequency compared to typical microcontroller or FPGA clocks. If some edge jitter is acceptable, i.e. only frequency accuracy is critical, this is the kind of problem that could easily be tackled by a single FPGA with eight counters and *8 /9 blocks.

    Regards,

  • 0 in reply to Derek Payne
    TI__Expert 8695 points

    Hi Derek，

    Thank you for your response.

    As you suggested we are actually working on a single FPGA and eight SN74LV4046A PLL.

    But "with eight counters and *8 /9 blocks" is not possible on FPGA(DPLL) as our input frequency is very less

    i.e.288 kbps (< 5Mhz).So we have to use PLL IC. Even two input clock signal PLL with two VCO output will hep us optimizing the board.

    Thanks.

  • 0 in reply to FRANK1
    TI__Mastermind 34270 points

    Hi FRANK1,

    If your jitter requirements are not very strict, your "DPLL" could be as simple as counting the number of FPGA oscillator cycles from one edge of the 288kHz clock to the next, multiplying that rate by 8/9, and reproducing the approximate 256kHz output signal from the corresponding number of FPGA oscillator periods. This would remain frequency-accurate on average since you would continuously update each clock with the input period, but the phase error is limited by the FPGA oscillator period; reduced phase error could be achieved with a faster FPGA oscillator, or by using the FPGA PLL to increase the clock rate of the counter measuring the 288kHz signal period.

    As I mentioned before, there are no other PLLs with multiple inputs that can operate at 288kHz input, and which are not highly overfeatured for this application. The closest option would be something from the network synchronizers portfolio like LMK5C33216, with three DPLLs, 16 outputs, and 1500 registers; the device also requires external XO. All other PLLs are limited by the minimum loop bandwidth, the divider value, or the input count.

    Regards,