SN74LV574A: Regarding IC operation

Shotaro Sakai

Part Number: SN74LV574A
Other Parts Discussed in Thread: SN74LVC574A, SN74AUP2G14

Hello team,

My customer has a question for SN74LV574A.

The data sheet says that data is output when CLK rises when OE is L, but does it work properly even if OE and CLK rise from L to H at the same time?

Is there a time constraint between OE and CLK, for example, how many ns the OE must be in the L state after the rise of CLK?

Best regards,

Shotaro

over 4 years ago

0 Clemens Ladisch over 4 years ago

Guru 317000 points

The datasheet says:

OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The switching characteristics table shows how long CLK and OE might take to affect the output pin.

t_dis is always smaller than t_pd, so when CLK and OE rise at the same time, the output will be disabled before the new data would be visible.

t_en is approximately the same as t_pd, so when CLK rises and OE falls at the same time, the old value might be visible for a very short time. (But it's probably not long enough for the output to switch completely.)

0 Shotaro Sakai over 4 years ago in reply to Clemens Ladisch

TI__Expert 3390 points

Thank you for reply.

Will the displayed data be updated when CLK starts up while OE is L?

0 Clemens Ladisch over 4 years ago in reply to Shotaro Sakai

Guru 317000 points

When there is a rising edge on CLK while OE is low, the output pins will be updated immediately (after t_pd).

0 Shotaro Sakai over 4 years ago in reply to Clemens Ladisch

TI__Expert 3390 points

Thank you for supporting.

I receive additional questions from the customer. Can you answer the question too?

1. What kind of trouble is expected when the signal input to OE and CLK becomes a metastable (an unstable state where the output is neither High nor Low)?

2. Also, is there a possibility or condition that the output of SN74LV574A itself becomes a metastable?

0 Clemens Ladisch over 4 years ago in reply to Shotaro Sakai

Guru 317000 points

See [FAQ] How does a slow or floating input affect a CMOS device? Please note that an input pin with a metastable voltage could cause other inputs to read a wrong value.

Flip-flop outputs indeed can become metastable; the LV family is quite bad:

If metastability is a concern, consider using the SN74LVC574A instead.

0 Shotaro Sakai over 4 years ago in reply to Clemens Ladisch

TI__Expert 3390 points

Thank you for supporting!

I sent your suggestion to the customer. But we don't clear the below points... An issue is happened in a released system implemented of SN74LV574A...

1. "read a wrong value" means the output is oscillating. Is this right?

2. Please tell me the conditions under which the metastable occurs at SN74LV574A. (OE or CLK is near the threshold?)

Or are there any other timing restrictions?

0 Clemens Ladisch over 4 years ago in reply to Shotaro Sakai

Guru 317000 points

1. Not only can the output oscillate, but other parts of the device can be affected. I have seen a report of a SN74AUP2G14, where one gate's input was floating, and the other gate appeared to behave like a non-inverting buffer.

2. A metastable state can happen only when the setup/hold times are violated (see Metastable Response in 5-V Logic Circuits). There is no such problem with OE; the outputs are correctly enabled/disabled as soon as OE has reached a valid voltage.

0 Shotaro Sakai over 4 years ago in reply to Clemens Ladisch

TI__Expert 3390 points

Thank you for supporting.

I have a request Regarding "1.".

Can you find for the report of SN74LVC2G14 you mentioned? It's helpful for explaining to the customer.

0 Clemens Ladisch over 4 years ago in reply to Shotaro Sakai

Guru 317000 points

electronics.stackexchange.com/questions/529602/logic-gates-not-working-as-expected

0 Shotaro Sakai over 4 years ago in reply to Clemens Ladisch

TI__Expert 3390 points

I got additional questions about SN74LV574A. Could you give me your opinion?

1. What will happen to the output if the OE is turned on and off in a very short time (Tdis, Ten) or less?

2. What will happen if the OE signal neither High nor Low is input?

0 Clemens Ladisch over 4 years ago in reply to Shotaro Sakai

Guru 317000 points

1. The output might become active for a short time.

2. See [FAQ] How does a slow or floating input affect a CMOS device?

0 Shotaro Sakai over 4 years ago in reply to Clemens Ladisch

TI__Expert 3390 points

Thank you for reply.

For #2, you mean Oscillation is happed when "signal for OE" is between the LOW and HIGH state, right?

0 Clemens Ladisch over 4 years ago in reply to Shotaro Sakai

Guru 317000 points

Yes.

0 Shotaro Sakai over 4 years ago in reply to Clemens Ladisch

TI__Expert 3390 points

Thank you for supporting.

I got additional question from the customer. Can you answer them?

1. Is the data displayed when CLK starts up when OE is L updated?

2. Does "The output might become active for a short time." mean output is enable?

3. For example, when OE is input and the output is switched from High to Low, if the input time of OE is very short, the output returns to the High state while changing from High to Low, and it is neither High nor Low for a moment. Is there a possibility that will be output?

0 Shotaro Sakai over 4 years ago in reply to Shotaro Sakai

TI__Expert 3390 points

Can you answer the above questions??

The customer is waiting for our response.

0 Clemens Ladisch over 4 years ago in reply to Shotaro Sakai

Guru 317000 points

Sorry; the notification got lost during the E2E upgrade.

1. As shown in the function table, when /OE is low, a rising clock edge will copy the data input to the output.

2. Yes.

3. When /OE changes, the output changes between off (Hi-Z) and the current state of the flip-flop. When the flip-flop changes from high to low, then the output can change from high to low. If the output is enabled/disabled at the same time, it is possible that the low or high state is not visible at the output, but it is never possible that the output goes from low to high.

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SN74LV574A: Regarding IC operation