[FAQ] What is the difference in timing between gates in the same device? How much skew is expected within a given logic device? What is the part-to-part skew?

FAQ: Logic and Voltage Translation > Timing Parameters >> Current FAQ

The difference in delay between the individual channels on an individual part is referred to as channel-to-channel skew or output skew. This is typically not covered as a datasheet parameter for logic devices.

Some logic devices may contain a t_sk specification in the datasheet, please refer to this specification in the switching characteristics table for the skew measurement.

For any TI logic devices that do not specify a skew parameter, we guarantee that the skew will be ≤ 1ns typical between any channel outputs at any one temperature. While across all temperatures the difference is up to ~3ns. Keep in mind that this applies to a single chip with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads.

The following plot from one of our E2E posts explains what is meant by this 1ns typical channel to channel skew: 

Here is the what to expect for typical max skew based on technology. These are not guaranteed though:

 - TTL = 800ps
 - Bicmos  = 500ps
 - CMOS is 250ps

We do not guarantee any part-to-part skew, however if they are from the same batch then typically they should also be limited to 1ns part to part skew.

Looking for a low voltage translator? Check out the AXC family that supports 0.7V to 3.3V translation!

The Logic Minute training page has videos on many interesting topics that all are kept shorter than 5 minutes.