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Original question:

TMS570LC4357: DCAN Bit Error Detection to ESM

TMS570LC4357: DCAN Single Bit ECC Error Detection issue

dhana lakshmi1
Prodigy 120 points
Part Number: TMS570LC4357


We are implementing DCAN ECC testing for single bit and double bit error detection. Referring and using SafeTI Diagnosis Library code in our implementation.

Double bit ECC error works fine but for single bit type works for only first call any DCAN(1/2/3/4), and when we call DCAN ECC self-test for single bit ECC function 
second time it set only the DEFLG (double bit flag) in ECC CS register and not SEFLG(single bit flag).
Could you please help why it set double bit and not single bit. 

  • 0
    TI__Guru**** 199006 points

    Hello Dhana,

    The SEFLG will not be set if the signal-bit ECC error is detected at the same location as the last single-bit error. 

    But the DEFLG should not be set for a single-bit ECC error.

  • 0 in reply to QJ Wang
    Prodigy 120 points

    Hi Wang,

    Thank you for your response. Using different dcanrambase addresses for 4 DCANs and also tried to read in different ram locations.
    Still see single bit ECC test is not working. And observed it works fine when _memInit_ function is called after each DCAN ECC test.
    But it clears all previous global data.

    Could you please suggest, how to use different locations to set ecc errors for each DAN when testing all 4 DCAN ECC tests are done one after other.

    Thanks

    Dhanalakshmi

  • 0 in reply to dhana lakshmi1
    TI__Guru**** 199006 points

    Yes, before accessing the DCAN message RAM, it should be initialized first to void the ECC error.

    If you use the SL_DCAN_Selftest() of safety diagnostic library, it is not easy to inject ECC to different locations. You can write your own code to inject ECC error:

    volatile uint32* data;

    for (i=1; i<3; i++){

         data = (volatile uint32 *)(canRAM1+  i * 0x20u + 0x4);

         canREG1->CTL = 0x5 << 10;  //PMD=0x5, disable SECDED

         canREG1->CTL |=  ( 1 << 7); // enable test mode

         canREG1->CTL |= (1 << 0) //init bit

         canREG1->TEST |=  (1 << 9); //enable direct access to RAM

         canREG1->ECCDIAG = 0x5; //enable ECC diag mode

         canREG1->ECC_CS = 0x5 << 24;  //enable SECDED single bit error 

         canREG1->CTL &= ~(0xF << 10);

         canREG1->CTL |= (0xA << 10);  //enable SECDED

         daraRead = *data;

         check the ESM register and CAN status register;

         clear the error flag

       }

    You will see the error for the 2nd location

  • 0 in reply to QJ Wang
    Prodigy 120 points

    Hi Wang,

    Thank you. I tried with below line instead of safety  library (sl_selftest.c) code line [ data = (volatile uint32 *)((((uint32)dcanRAMBase) + (msgNo*0x20u)));
    data++; ] and it works fine now for all DCAN single bits. I observed typecasting dcanRAMBase with uint32 in sl_selftest.c code increase offset by 1 byte (32-bit) and below one increase offset by 4 bytes.  For example if dcanRAMBase address =  0xFF1E0000; with below line of code offset changed to 0xFF1E0110 instead of 0xFF1E0044 and that works. 

    data = (volatile uint32 *)(canRAM1+ msgNo  * 0x20u + 0x4); where msgNo = 2u

    Thanks

    DhanaLakshmi