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TMS570LC4357: DCAN Bit Error Detection to ESM

Max Wittekind
Expert 1835 points
Part Number: TMS570LC4357

Hello Experts,

The Safety Manual mentions the CAN13 Bit Error Detection which, if I understand correctly, refers to the SECDED of the DCAN-Modul.
According to the Reference Manual single- and double bit errors can generate an interrupt and the error bits are set.

Additionaly the Data Manual list ESM 1.21, 1.22, 1.23, 1.51, 1.73, 1.74, 1.75 and 1.76 beeing set on bit error. However there is no mention of an error getting signaled to the ESM in the Reference Manual.

(Q1) Will the DCAN always signal the ESM that a bit-error has ocurred or is there a way to configure this?

Thank you and best regards,
Max

  • 0
    TI__Guru**** 193046 points

    Hi Max,

    You are correct. The DCAN module provides SECDED mechanism to ensure data integrity of DCAN message RAM. If single-bit or double-bit ECC error occurs, the SEFLG bit or DEFLG in ECC CS register will be set, and the interrupt will be generated if the error interrupt is enabled.

    ESM1.73 (DCAN1 single-bit error) is set if a signal-bit ECC error happens and the SECDED is enabled. The SECDED can be enabled by writing any value other than 0x5 to PMD field of DCAN CTL register.