TMS570LC4357: VIM ECC test triggers ESM 1.83 and 1.15 when injecting single bit error

Hi Max,

You are correct. The ESM 1.15 should not be set if only SBE is detected.

Which rev silicon do you use? There is one HW bug on RevA silicon: VIM#28. (single bit error is treated as UERR too).

Hi QJ,
We checked the boards and both silicons are RevB (TMS5704357BZWTQQ1).

I tested on RevB silicon this morning. 

When 1bit of ECC value (at 0xFFF82400) or VIM data (at 0xFFF82000) is flipped, reading data sets ESM 1.15 and ESM 1.83, VIM ECCStatus=0x101

When 2 bit of ECC value or data are flipped, reading data only sets ESM 1.15, VIM ECC status = 0x001

I don't know why the UERR flag is set.

Hi QJ,

So is it save to assume, that this will happen everytime we test the ECC?

If this is the case,  we can just check for both errors on single bit diagnostic.