TMS570LC4357-EP: VIM RAM fault injection: ESM ISR not being cleared

Hi all,

First off, apologies if this ends up in the wrong forum. I navigated to the Hercules forum and attempted to create a new thread, but the moment I use the actual part number I'm using, it appears my post gets assigned to "Other microcontrollers forum".

Question/issue 1:

In any case, I'm facing an issue performing fault injection of a correctable (i.e. single-bit) error into some word within the VIM RAM address space. I have generated a project in Halcogen where I enable ESM Group 1 line 83 (which as I understand it is the correctable VIM RAM ECC error.) I also verified VIM RAM ECC is enabled under VIM configuration. I set the ESM group 1 line 83 error to assert an ESM low-level IRQ (i.e. not FIQ) event, and then output some debug info within the esmGroup1Notification callback provided by Halcogen in HL_notification.c

To trigger the ECC error, I followed the procedure set out in the TMS570LC4357 TRM VIM chapter:

- I make sure ECCENA is set and VIM RAM has been initialized. (This is handled already by vimInit() which I call from main())

- I then enable ECC bits mapping by writing 0x5 << 8 into ECCCTL (more specifically, I write the absolute mask: 0xA << 0 | 0x5 << 8 | 0xA << 16 | 0xA << 24 into ECCCTL)

- Following this, I have tried either reading a word within the VIM ECC address space (which I map with a volatile struct containing an array of u32 entries), flipping one of the 6 LSBs, and writing that word back.... -or- doing the same but to vector entries within the VIM RAM itself.

In both of the above cases, I get an IRQ and vector to the esmGroup1Notification (from the esmLowInterrupt within HL_esm.c). When I print out the channel argument, I can see that it's correct (when I add back the offset the ISR took off, I see it's a notification for ESM channel 83). However, it seems the ISR keeps being called repeatedly, and I can't escape from the interrupt context. This is despite looking through TI's ISR code, where it's clear the ISR is clearing the error flag correctly by writing 1<<19 to SR4, as per the TRM.

For completeness, I am using Halcogen 04.07.01, targeting GCC tools. I am using GCC 10.2, built from the standard upstream crosstool-ng project, with the necessary big-endian multilib support.

The Halcogen project is the standard TMS570LC43x-targeted project, with the LIN1 High, RTI Compare 0 and ESM Low-level IRQs enabled. 

Thanks!

- AG