Original question:
hi，For SRAM diagnosis, ECC is enabled in the cycle diagnosis. The yellow part in the figure below cannot be selected.
（1）What do these three diagnosis items mean?
（2）ECC diagnosis can guarantee soft failures（软失效）, so how to guarantee hard failures（硬失效）?
Thanks a lot.
Hi Xiaohong,
Those three mechanism are enabled by default and can not be disabled.
1. RAM 2:
Livelock: Livelock is a state in which the processor pipeline is advancing and executing instructions, but the processor is repeatedly executes the same instruction so that it makes no progress through the program. When you have an underfined instruction at the undefined exception vector at 0x04 the processor can never advance the program flow and hence raises the livelock event. When ESM receives the livelock event, it is able to create an asynchronous exception (e.g. a NMI interrupt) to the processor in a normal way.
Hard error cache: The hard error cache is implemented inside the CPU core. The hard error cache is a one-entry cache where it records the memory location that has a correctable error. Let's suppose the SRAM has defect at one location, when CPU reads from this location again it will have the same error and this will go on forever if there is no hard error cache. The first time an correctable error in the SRAM is detected the memory location is recorded in the hard error cache. If CPU reads from the same address again it first check against the hard error cache to see if there is a matching address. If there is a match it will not generate error.
2. RAM6:
Each logical SRAM word and its associated ECC code is split and stored in two physical SRAM banks. Each access comprises 72 total bits - 64 bits of data and 8 bits of ECC code. This scheme provides an inherent safety mechanism for address decode failures in the physical SRAM banks. Faults in the bank addressing are detected by the CPU as an ECC fault.
3. RAM8:
The SRAM module supports bit multiplexing scheme. The bits of the content at one SRAM location are not physically adjacent. For example, the bit 1 is not next cell of bit 0.
This scheme helps to reduce the probability of physical multi-bit faults resulting in logical multi-bit faults.
