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RM57L843: Diagnostic library SL_SelfTest_SRAM fails

Koichiro Tashiro
Mastermind 22435 points
Part Number: RM57L843

Hi,

My customer implement SRAM self test using Diagnostic Library 2.4.0.

Check RAM ECC:

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boolean retVal;
SL_SelfTest_Result result;
retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_1BIT, TRUE, &result);
if(retVal == false){while(1);}
if(result != ST_PASS)
{
/* Test fail */
while(1);
}
retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_2BIT, TRUE, &result);
if(retVal == false){while(1);}
if(result != ST_PASS)
{
/* Test fail */
while(1);
}
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX


Check Flash ECC:
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boolean retVal;
SL_SelfTest_Result result;
/* Flash test needs to be run from a RAM location. Copy flash test to RAM */
uint32 i;
uint32 size=(uint32)&ulHighHandlerSize;
for(i=0;i<size;i++)
{
((char *)&ulHighHandlerStartAddr)[i] =((char *)&ulHighHandlerLoadStart)[i];
}
retVal = SL_SelfTest_Flash(FLASH_ECC_TEST_MODE_1BIT, TRUE, &result);
if(retVal == false){while(1);}
if(result != ST_PASS)
{
/* Test fail */
while(1);
}
retVal = SL_SelfTest_Flash(FLASH_ECC_TEST_MODE_2BIT, TRUE, &result);
if(retVal == false){while(1);}
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX


But all tests failed and stuck in the while loop.

        if(result != ST_PASS)

        {

            /* Test fail */

            while(1);

        }

The code seems correct. What is missing here?

Thanks and regards,
Koichiro Tashiro

  • 0
    TI__Guru**** 193286 points

    Hi Koichiro-san,

    When the test completes, are the error flags in RAM status register and ESM status register set correctly?

    For SRAM_ECC_ERROR_FORCING_2BIT test, the ESM 2.7, and RAMERRSTATUS[21:20] should be set. Can you please check bit is not set after your self-test?

  • 0 in reply to QJ Wang
    TI__Mastermind 22435 points

    Hi QJ,

    QJ Wang said:
    When the test completes, are the error flags in RAM status register and ESM status register set correctly?

    After 
    retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_1BIT, TRUE, &result);
    retVal = 0 and
    esm1_stat1 : 00000000
    esm1_stat2 : 00000000
    esm1_stat3 : 00000008
    L2ramw_RamErrStat：00000080    00000000        00000000        00000000

    After
    retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_2BIT, TRUE, &result);
    retVal =0 and
    esm1_stat1 : 00000000
    esm1_stat2 : 00000000
    esm1_stat3 : 00000008
    L2ramw_RamErrStat：00000080    00000000        00000000        00000000

    Thanks and regards,
    Koichiro Tashiro 

  • 0 in reply to Koichiro Tashiro
    TI__Guru**** 193286 points

    Hi Koichiro-san,

    Just run a test using the SDL on RM57Lx HDK:

    1. retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_1BIT, TRUE, &failInfoTCMRAM);

    ESMSR2 = 0x80   --> ESM 2.7 = 1

    DRSE=1, Diagnostic Read Single-bit Error.

    and DWSE=1, Diagnostic Write Single-bit Error

    2. retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_2BIT, TRUE, &failInfoTCMRAM);

    DRDE=1, and DWDE=1  (RAMERRSTATUS register)

  • 0 in reply to QJ Wang
    TI__Mastermind 22435 points

    Hi QJ,

    Thanks for trying.
    Your results are different than what customer got.
    I guess something different between your test and customer's.
    Could you send me your source code?

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Guru**** 193286 points

    Hi Koichiro-san,

    I use the example code in the SDL folder. I added two function calls in the main():

    I set two breakpoints at those two function calls, and step into the SL_Selftest_SRAM(..), and check the ESM status registers and L2RAM Error register before the error flags are cleared.

    To simply my test, I disable the CPU selftest in _c_int00().

  • 0 in reply to QJ Wang
    TI__Guru**** 193286 points

    This is the app_main_NoOS.c and HL_sys_startup.c used for my test:

    All edited code has comment of "//QJ" 

    0602.app_main_NoOS.c

    4505.HL_sys_startup.c
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    /** @file HL_sys_startup.c
    * @brief Startup Source File
    * @date 02-Mar-2016
    * @version 04.05.02
    *
    * This file contains:
    * - Include Files
    * - Type Definitions
    * - External Functions
    * - VIM RAM Setup
    * - Startup Routine
    * .
    * which are relevant for the Startup.
    */
    /*
    * Copyright (C) 2009-2016 Texas Instruments Incorporated - www.ti.com
    *
    *
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to QJ Wang
    TI__Mastermind 22435 points

    Hi QJ,

    Unfortunately SL_SelfTest_Flash() does not pass in customer environment.
    The code stops at below:

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    retVal = SL_SelfTest_Flash(FLASH_ECC_TEST_MODE_2BIT, TRUE, &result);
    if(retVal == false){while(1);}
    if(result != ST_PASS)
    {
    /* Test fail */
    while(1); <== code stops here
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX


    Customer checked sl_selfttest.c and found it failed at line#1311.
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    if (BIT(ESM_G2ERR_CR5_BUSERR) == (sl_esmREG->SSR2 & BIT(ESM_G2ERR_CR5_BUSERR))) {
    /* Clear nError */
    _SL_HoldNClear_nError();
    sl_esmREG->SSR2 = BIT(ESM_G2ERR_CR5_BUSERR);
    *flash_stResult = ST_PASS;
    } else {
    *flash_stResult = ST_FAIL; <== ST_FAIL returned here
    }
    }
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX


    What is potential reason it fails here?

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Guru**** 193286 points

    Can you disable the pipeline before triggering the diagnostics and re-enable it after the test?

    sl_flashWREG->FDIAGCTRL |= F021F_FDIAGCTRL_DIAG_TRIG;

    /* disable pipeline mode*/

    sl_flashWREG->FRDCNTL &= 0xFFFFFFFE;

    flashread = *(volatile uint32 *)flashBadECC2;

    /*Enable pipeline mode*/

    sl_flashWREG->FRDCNTL |= 0x01;