Hello,
as I am currently writing an abstraction for GPIO pins on top of your MCU+ SDK,
I am trying to understand the calculation of the bank and pin addresses.
In the Technical Reference Manual "AM64x /AM243x Processors Silicon, Revision 1.0" it says in "12.1.2.1 GPIO Overview" :
"...
The device has three instances of GPIO modules. The GPIO pins are grouped into banks (16 pins per bank
and 9 banks per module), which means that each GPIO module provides up to 144 dedicated general-purpose
pins with input and output capabilities; thus, the general-purpose interface supports up to 432 (3 instances × (9
banks × 16 pins)) pins.
..."
As I understand it the base address that needs to be provided in drivers/gpio/v0/gpio.h in functions like GPIO_pinWriteHigh, GPIO_pinWriteLow, GPIO_pinRead, etc.
Is the address of the module/instance which is represented by a CSL_GpioRegs structure.
The bank index is then calculated using GPIO_GET_REG_INDEX(pinNum) and the pin bit position within the bank register using GPIO_GET_BIT_POS(pinNum).
The code generated by SysConfig then defines CSL_GPIO0_BASE and CSL_GPIO1_BASE. I guess those are the modules/instances base addresses.
Is that correct?
The part where I am getting confused here is that in Sysconfig I can only choose GPIO0 and GPIO1
But in the reference manual it said that there are 3 modules/instances. Shouldn't there be GPIO2 as well? Or maybe I am wrong to assume that those are the base addresses of the modules/instances after all?
Thank you for your time and trouble.
Best regards
Philip.
