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LAUNCHXL2-RM57L: CCM-R5F module reporting to the ESM

Phadon Phipat
Prodigy 50 points
Part Number: LAUNCHXL2-RM57L

Hi,

I am having troubles running self-tests, error-forcing mode and self-test error forcing mode on the CCM-R5F module.

For self testing, I am writing 6h into the CCMKEYR1 to CCMKEYR4 registers and then waiting for 100ms. I have tried writing in them separately and varying the wait time, however after this procedure when I read in the relevant status register (CCMSR1 to CCMSR4), I never see the self-test-complete bit as a 1. The entire status register is 0. I do however see that when write 6h to CCMKEYR1, that the CPU Compare module goes out of lockstep as I get a channel 92 CCM operating status error in my ESM.

For error-forcing mode, I am writing 9h into the key registers, and then waiting for 100ms.  Again, all the status registers show up as 0. I do not get any ESM errors for key registers 1-3. When I write to CCMKEYR4, the Power domain inactivity monitor, I get a group 1 channel 31 ccm self test error and a .group 2 channel 28 ccm power domain monitor error. This seems to be the correct behaviour I that I expect to see with the other three registers, although the status register is still 0.

For self-test-error-forcing mode I am writing Fh into the key registers and then waiting 100ms. I see similar behaviour to error-forcing mode. The status registers are always 0 at the end, and key registers 1-3 do not output any error to the ESM. For key register 4, I get a CCM self test error from the ESM.

Am I going about these tests the wrong way or is there a step I am missing? Any help or guidance would be much appreciated.

Thank you

  • 0
    TI__Guru**** 192486 points

    Hi,

    You are running self-test for comparing the CPU outputs compare logic, VIM outputs compare logic, CPU inactivity logic, and power domain inactivity logic at a time. Can you separate those test?

  • 0 in reply to QJ Wang
    Prodigy 50 points

    Yes, I have already tried this and the same behaviour occurs.

  • 0 in reply to QJ Wang
    TI__Guru**** 192486 points

    I just did CCM self-test, and it only takes 4000 CPU cycles (13us).

  • 0 in reply to QJ Wang
    Prodigy 50 points

    Thanks a lot for the help and code. I implemented this code in our main function. From what we can see, only CCMSR4 is set. If we leave the code running, it gets blocked at the first while loop. 

    Attached is c_int00() code that runs before main(). Is there anything in here that we are doing wrong?

    c_int00.c
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    void _c_int00()
    {
    /* Initialize Core Registers to avoid CCM Error */
    _coreInitRegisters_();
    /* Initialize Stack Pointers */
    _coreInitStackPointer_();
    /* Reset handler: the following instructions read from the system exception status register
    * to identify the cause of the CPU reset.
    */
    switch (getResetSource())
    {
    case POWERON_RESET:
    case DEBUG_RESET:
    case EXT_RESET:
    case OSC_FAILURE_RESET:
    case WATCHDOG_RESET:
    case WATCHDOG2_RESET:
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to Phadon Phipat
    TI__Guru**** 192486 points

    Hi,

    Can you try my HL_sys_startup.c?

    3414.HL_sys_startup.c
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    /** @file HL_sys_startup.c
    * @brief Startup Source File
    * @date 11-Dec-2018
    * @version 04.07.01
    *
    * This file contains:
    * - Include Files
    * - Type Definitions
    * - External Functions
    * - VIM RAM Setup
    * - Startup Routine
    * .
    * which are relevant for the Startup.
    */
    /*
    * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
    *
    *
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX