Good morning,
I have yet another question concerning GPIO.
What I understand:
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The pins on our board are currently configured using SysConfig which generates a map of type gPinMuxMainDomainCfg with pin name
(which is the pins offset defined in TI_sdk/mcu_plus_sdk_am64x/source/drivers/pinmux/am64x_am243x/pinmux.h in enum Pinmux_MainOffsets)
as key and settings (PIN_MODE, pull direction, input/output) as data.
During initialization a function Pinmux_Init is called which calls itself Pinmux_Config once with domain main and once with domain mcu.
Then inside Pinmux_Configgiven a domain (main or mcu). Then the base address is calculated from the domain.
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What I don't understand
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Now it seems that each single pin can somehow be accessed from a domain dependant base address and the pin offset given in enum Pinmux_MainOffsets.
This includes GPIO-pins.
But at the same time, GPIO-pins are accessed only as a bit position (whcih makes sense as they only have a digital value) from calculating bank register index and pin mask
from GPIO module base address which points to a CSL_GpioRegs struct defined in TI_sdk/mcu_plus_sdk_am64x/source/drivers/gpio/v0/cslr_gpio.h.
And my problem here is that I don't see how the Sysconfig approach with registers for each pin and the cslr_gpio.h approach with registers only for banks and pins as bit values fit together.
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Thank you for your time and trouble.
Best regards
Philip.
