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TMS570LS3137-EP: Keep track of error count after resets

Sagar S
Prodigy 40 points
Part Number: TMS570LS3137-EP
Other Parts Discussed in Thread: TMS570LS3137, TMS570LS1224

Hi,

I have certain errors after they occur for multiple times I would want to assert the nError pin by writing to the register. The errors are not present in the ESM group.

On each occurrence of the error I would perform a warm reset and retry the test detecting the error, after certain number error counts I would assert the nError.

How can I keep track track of the error count after each reset?

Is there any general purpose registers which holds value after reset?

  • 0
    TI__Guru**** 191886 points

    Hi Sagar,

      There are no general purpose registers which are not affected by reset. In another word, a reset will clear pretty much all registers in the device except for a few status registers which are not writable by users. 

      What I can suggest is that you use the unused peripheral RAM such as VIM RAM or NHET RAM to store your error count. Of course, you could also save the error count in the system SRAM but you need to be aware that if your SRAM is subject to PBIST memory test then the data will be wiped out in your startup after reset. In that case, before you start PBIST test, first move your error count data from SRAM to some peripheral RAM before you start PBIST and then restore the data after memory test. 

  • 0
    Prodigy 40 points

    Hi Charles thanks for the suggestions.

    I am trying the VIM RAM option. The VIM RAM address range is 0xFFF82000 to 0xFFF82FFF. 96 interrupt channels occupy addresses up to 0xFFF8217D.

    The remaining addresses is what I am trying to use but they are not writable. Can addresses above 0xFFF8217D be used or are they protected/used for something else?

  • 0 in reply to Sagar S
    TI__Guru**** 191886 points

    Hi Sagar,

      I just tried to write to the last entry (the 96th entry) in the VIM RAM at 0xFFF823FC and no issue clearing this location to zero in CCS. 

      Please also be aware that I will be out of office and won't be able to reply until next year for any questions that involves debugging. 

  • 0 in reply to Charles Tsai
    Prodigy 40 points

    Hi 

    There is a below thread which discourages using SRAM data after reset:

    https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/912602/tms570ls3137-non-volatile-ram-for-software-reset

    Please suggest whether using SRAM to store and use data after a reset a reliable method?

    Does performing CRC of the SRAM data after reset solve reliability problem?

  • 0 in reply to Sagar S
    TI__Guru**** 191886 points

    Hi,

      The reason QJ in the other post was cautious to use data in SRAM after a reset cycle was because a "uncontrolled" reset event in the middle of a write operation to SRAM can corrupt the memory content. The warm reset that you are going to perform is part of your startup diagnostic is a controlled event by your software. Therefore, I don't believe you will experience corruption to the memory. An example of an uncontrolled reset could be a nRST assertion from your external logic in the middle of a SRAM write operation. This can corrupt the memory.  

  • 0 in reply to Charles Tsai
    Prodigy 40 points

    Hi Charles,

    Yes, 0xFFF823FC can be written.

    But the idea was was not to use the VIM RAM area reserved for 96 interrupt channels, rather use the region after it (between 0xFFF8217D to 0xFFF82400).

    I observe that we cannot write in the region 0xFFF8217D to 0xFFF82400. Is this region reserved for something else?

    Also, please let know is there any advantage of using peripheral RAM (VIM RAM) over SRAM?

  • 0 in reply to Sagar S
    Prodigy 40 points

    Thanks for clarifying.

  • 0 in reply to Sagar S
    TI__Guru**** 191886 points

    Hi Sagar,

      I try in CCS to modify some of the last locations in VIM RAM and don't see an issue. 

    Sagar S said:
    Also, please let know is there any advantage of using peripheral RAM (VIM RAM) over SRAM?

    The reason I suggested VIM RAM was because if you run PBIST for SRAM in your startup the SRAM can be wiped although that is also true for VIM RAM if you enable PBIST to run memory test on VIM RAM.

  • 0 in reply to Charles Tsai
    TI__Guru**** 191886 points

    I should also say that I was testing on another device TMS570LS1224 as I don't have TMS570LS3137 with me at the moment. TMS570LS1224 has VIM RAM that can support 128 channels while TMS570LS3137 only has VIM RAM to support 96 channels. This is the reason beyond 96 channels, there is no physical memory. But you should still be able to write the last few locations of VIM RAM as they are not used.