TMS570LC4357: Due core assign task and synchronisation

Kishor Vitalkar

Part Number: TMS570LC4357
Other Parts Discussed in Thread: AM2434

Hi,

As you mentioned on one of thread that Duel core is enabled by default, I would like to know how can I assign task to core1?

How to synchronize both cores? and please suggest optimism method for IOC and how to achieve data consistency. It will be great if you refer some example.

Kind Regards,

Kishor

over 3 years ago

0 Frank Livingston over 3 years ago

TI__Mastermind 29348 points

Hi, our expert is out of the office for several days. Please expect a delayed response.

0 QJ Wang over 3 years ago in reply to Frank Livingston

TI__Guru**** 196776 points

Hi Kishor,

The dual CPUs are in lockstep which means that two cores are running the same set of instructions in parallel. This architecture provides cycle by cycle checking of correct CPU operation while keeping a simple, easy to use single core programmer's model. The two cores are synched. When you run the code, the instruction is loaded to both cores automatically and run in parallel. The outputs of two cores are fed to comparator (CCM-R4F module) to look for single point faults.

0 Kishor Vitalkar over 3 years ago in reply to QJ Wang

Prodigy 120 points

Hello Frank, thank you for reply " easy to use single core programmer's model" is that mean there is no way to access cores separately? And it can not be used to divide MCU load am I correct?

How to test and identify occurrence of single point fault event?

How it can be configure or use for expected output on SPF event?

Regards,

Kishor

0 Chester Gillon over 3 years ago in reply to Kishor Vitalkar

Guru 92251 points

Kishor Vitalkar said:
And it can not be used to divide MCU load am I correct?

The ARM design for a Cortex-R5 processor group of two CPUs allows for either:

Split mode

Operates as a twin-CPU configuration. Also known as performance mode.

Locked mode

Operates as a redundant CPU configuration. Also known as safety mode.

A TMS570LC4357 only operates in Locked Mode (lockstep).

Whereas some other TI processors using a Cortex-R5 allows the user to switch a Cortex-R5 processor group between either lockstep (two cores in lockstep) or split mode (two independent cores). E.g. an AM2434.

0 QJ Wang over 3 years ago in reply to Chester Gillon

TI__Guru**** 196776 points

Thanks Chester.

Yes, AM24x and AM26x support both split mode and lockstep mode. But TMS570 supports lockstep mode only.

0 Kishor Vitalkar over 3 years ago in reply to QJ Wang

Prodigy 120 points

Thank you very much for clarification.

Arm-based microcontrollers

Arm-based microcontrollers forum

TMS570LC4357: Due core assign task and synchronisation