TMS570LC4357: TMS570LC4357 Lock Step CPU Operation

Tarun Sharma

Part Number: TMS570LC4357

Hi TI AE Team,

I wanted to understand operation of TMS570LC4357 dual core CPU in lockstpe operation in detail. Reading through datasheet and reference manual; I get the impression that CPU are internally linked and cannot be controlled independently. Can TI AE confirm that?

Thanks,

tarun172

over 4 years ago

0 Frank Livingston over 4 years ago

TI__Mastermind 29808 points

Hi, our expert is out of the office for several days. Please expect a delayed response.

0 Tarun Sharma over 4 years ago in reply to Frank Livingston

Prodigy 50 points

Hi Frank and TI team, good afternoon. I am following up on my request below. I wanted to confirm differences between R5 core implemented in Hercules architecture and R5 core.

https://dkc3.digikey.com/images/mkt/cortex/arm-cortex-r-technology-for-safe-and-relaible-systems.pdf

https://www.silabs.com/documents/public/white-papers/Which-ARM-Cortex-Core-Is-Right-for-Your-Application.pdf

Per link here, R5 core can be implemented as dual core. Please confirm.

Thanks,

tarun172

0 QJ Wang over 3 years ago in reply to Tarun Sharma

TI__Guru**** 199016 points

The lockstep implementation is composed of a functional core and a checker core. Software is written with a single core programmer's model. The two cores are fed same input signals and the outputs are compared.

The lockstep comparator compares the output signals of the functional core and the checker core in addition to a number of internal signals which ARM identified as critical to CPU state.

0 Tarun Sharma over 3 years ago in reply to QJ Wang

Prodigy 50 points

Hi QJ,

Thanks for clarifying. Just to confirm as a developer I do not have access to checker CPU correct?

Thanks,

tarun172

+1 QJ Wang over 3 years ago in reply to Tarun Sharma

TI__Guru**** 199016 points

No, we are not able to access the checker.

0 Tarun Sharma over 3 years ago in reply to QJ Wang

Prodigy 50 points

Thank you!

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TMS570LC4357: TMS570LC4357 Lock Step CPU Operation