TMS570LS1114: SRAM ECC single BIT diagnostic function

zhang xiaohong said:

(1) If a single BIT ECC error is found at a certain address, will the SECDED module rewrite the corrected data into SRAM? Do I mean to correct the original SRAM data, or just correct the read data?

The corrected data will be written to SRAM.

zhang xiaohong said:

(2) In SRAM diagnosis, the hardware provides Hard error cache and livelock functions. Is the function of Hard error cache to store the address of 1bit ECC failure?

zhang xiaohong said:

(3) If a 1-bit ECC failure occurs at a certain address, and then the SECDED module corrects it, then the Hard error cache will also record the address where the error occurred. If this address has a 1-bit ECC failure again, then the CPU By checking the Hard error cache, it is found that this address has failed, and no error alarm will be generated. Will the CPU continue to correct the wrong BIT bit on this address?

Yes, the hard error cache stores the address and corrected data. The purpose of the hard error cache is to prevent CPU from reading the SRAM or flash which have permanent single bit error. Let's say there is a defect in one of the memory cells. If you read from it the CPU will detect it as a single bit ECC error. What the CPU will try to do is to save the corrected data to the hard error cache and also write back the corrected to the SRAM or flash and then retry. Next time if the CPU reads from the same error address then it simply read from the cache instead of reading from the SRAM or flash since there is a match in the address. You can use the RAMTHRESHOLD register to setup the single bit threshold occurrences. Likewise, the FEDACCTRL2 register for flash to setup the occurrences threshold.

zhang xiaohong said:

(4) If a 1-bit ECC failure occurs in multiple addresses, will these addresses be recorded in the Hard error cache?

No, there is only one hard error cache inside the CPU. 

zhang xiaohong said:

If Later, a single-bit error also occurs at some other address, so this address will not be saved in the hardware error cache, right?

The new address and new corrected data are stored in the cache.

zhang xiaohong said:

If Later, a single-bit error also occurs at some other address, so this address will not be saved in the hardware error cache, right?

This address and corrected data will be stored into the cache.

zhang xiaohong said:

If the address has a permanent single-bit failure, then the single-bit error cannot be corrected in this case?

It will correct the single-bit error, and the corrected data and its address are stored in the cache.

Thanks for your reply,best regards.