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Original question:

TMS570LC4357: Regarding "Register Soft Error"

TMS570LC4357: Regarding High-Integrity bits of DMA module

Sho Kobori
Intellectual 640 points
Part Number: TMS570LC4357

HI,

This is a question regarding High-Integrity bits of DMA module and ESM1.88.

We already checked DMA module section of SPNU563A wasn't described detail about high-Integrity bits.

We would like to identify high-integrity bits of DMA module.

For example, SYS module was described as a following Section 2.5.1.13 of SPNU563A.

2.5.1.13 Clock Domain Disable Register (CDDIS)
NOTE: All the clock domains are enabled on wakeup.
The application should assure that when HCLK and VCLK_sys are turned off through the HCLKOFF bit, the GCLK1 domain is also turned off.
The register bits in CDDIS are designated as high-integrity bits and have been implemented with error-correcting logic such that each bit, although read and written as a single bit, is actually a multi-bit key with error correction capability. As such, single-bit flips within the “key” can be corrected allowing protection of the system as a whole. An error detected is signaled to the ESM module.

Could you please tell me which register corresponds to the high integrity bit.

Thanks,

Sho

  • 0
    TI__Guru**** 196306 points

    Hi Sho,

    The following DMA registers are protected by majority base safety protection logic (or high integrity):

    1. DMA_EN bit (bit 16) and DMARES bit (bit 0) in GLOBAL CONTROL Register (GCTRL)

    2. ERRA:bit (bit 16), TEST bit (bit 8) in DMA ECC CONTROL Register (DMAPECR)

    3. SBERR (bit 16) in DMA Single-Bit ECC Control Register (DMASECCCTRL)

    DMA_EN/ERRA/TEST/SBERR is one bit as shown in the registers but in actual design it consists of three bits. If one of these three bits flip, still DMA will look into the majority of these three bits and control bit will still be correct.

  • 0 in reply to QJ Wang
    Intellectual 640 points

    Hello QJ,

    Thank you for your reply.

    We could understand regarding High-Integrity bits of DMA.

    We have additional three questions about High-Integrity bits of L2FMC(ESM 1.89) and SYS(ESM 1.90).

    Q1. Could you please tell me which Bits and Register corresponds to the high integrity bit of L2FMC module?

    Q2. Which is bits of CDDIS, CPURSTCR and SYSECR on the SYS module protected by High-Integrity bits?

    Q3. Is there protected Bits by High-Integrity bits other than register of Q2?

    Thanks,

    Sho

  • 0 in reply to Sho Kobori
    TI__Guru**** 196306 points

    Hello Sho,

    Sho Kobori said:
    Q1. Could you please tell me which Bits and Register corresponds to the high integrity bit of L2FMC module?

    RCR_ERR bit of FEDAC_GBLSTATUS register. 

    Sho Kobori said:
    Q2. Which is bits of CDDIS, CPURSTCR and SYSECR on the SYS module protected by High-Integrity bits?

    CDDIS: All clock domain bits

    CPURSTCR: CPU RESET bit (bit 0)

    SYSECR: RESET[1-0] bits

    Sho Kobori said:
    Q3. Is there protected Bits by High-Integrity bits other than register of Q2?

    MPULOCK: lock bit

    MPUDIAGCTRL: DIAGKEY bits

    MPUCTRL1: MPUENA

    MPUCTRL2: ERRENA

  • 0 in reply to QJ Wang
    Intellectual 640 points

    Hello QJ,

    Thank you for your response.

    Is our understanding correct about operating of high-integrity bits below?

    1) Processing of Write to high-integrity bits

    High-integrity bits is configured each 3-bit, and each bit is same value(1 or 0).

    2) Processing of Read when occurred single-bit error 

    As a following figure of GCLK1OFF and VCLK3OFF, high-integrity bits is read correct value if one bit of 3-bits is flipping.

    3) Processing of read when occurred multi-bit error

    As a following figure of GCLK1OFF, high-integrity bits is read incorrect value if two bits of 3-bits is flipping, and ESM of "Register soft error" is generated.

    If our understanding is correct, how is Register Soft Error detected when flapped two bits of 3-bits?

    Thanks,

    Sho

  • 0 in reply to Sho Kobori
    TI__Guru**** 196306 points

    Hi Sho,

    Helpful diagrams. You are correct. Thanks

  • 0 in reply to QJ Wang
    Intellectual 640 points

    Hello QJ,

    Thank you for your response.

    We have a question about flipped bit of high-integrity bits.

    To notify ESM of 'Register soft error', these modules should detect to flipped 2bit of high-integrity bits.

    Could you please tell me about detection method of flipped 2bits?

    The following example expect GCLK1OFF of CDDIS register read the value of zero.

    Case 1) flipped 1bit, write = 0, read = 0

    Case 2) flipped 2bits, write = 1, read = 0

    Thanks,

    Sho

  • 0 in reply to Sho Kobori
    TI__Guru**** 196306 points

    Hi Sho-san,

    A single-bit flip within the “high-integrity bits” can be corrected, but two-bit or three-bit flips can not be corrected. In your example, the value of majority bits is 0, the return of read operation is 0.

    Your diagram is correct.

  • 0 in reply to QJ Wang
    Prodigy 10 points

    Hello QJ-san,

    Thank you for your response.

    I'm teammate with Sho.

    I have more questions.

    (1) I created a diagram about the relationship between "high-integrity bits" and "ESM". Is this correct?
    (2) If this image is correct,please tell me the contents of "Uncorrectable error detection logic".
    (3) If this image is NOT correct,please tell me about the relationship between "high-integrity bits" and "ESM".

    Best Regards,

    Teruhisa

  • 0 in reply to Teruhisa Takahashi
    TI__Guru**** 196306 points

    Hi Teruhisa,

    Your understanding is correct!