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AM2434: TMDS243GPEVM DDR Initialization

Part Number: AM2434

How many days does it take for the AM24_DDR_Initialization_ECC_Disabled GEL script to complete? I am running it on the TMD2243GPEVM development board, and it has been running for over 18 hours now.

  • Hi Paul,

    Use the SBL NULL is the recommended way to initialize the DDR. There is a catch though. The SBL NULL from MCU+ SDK of AM243x does not initialize the DDR. The SBL NULL from MCU+ SDK of AM64x does initialize the DDR. So download the latest MCU+ SDK AM64x and use the SBL_NULL from C:\ti\mcu_plus_sdk_am64x_08_01_00_36\tools\boot\sbl_prebuilt\am64x-evm\sbl_null.release.tiimage for OSPi flash write or SD card boot. It will do the DDR initialization for you. No need to use GEL file.

    Best regards,

    Ming

  • Will this file execute on the AM2434, which is on the TMD2243GPEVM? If it contains 64-bit instructions, I don't see how it will work.

  • Hi Paul,

    The AM243x 17x17 (on AM243x EVM) is the same as the AM64x (on AM64x EVM), plus the sbl_null.release.tiimage is actually runs on R5F_0_0 (which uses the 32 bit instructions), so it is perfectly OK to run the sbl_null.release.tiimage for AM64x on AM243x.

    To try it quickly without write to your OSPI flash, you can use the SD card boot option. See AM64x MCU+ SDK: EVM Setup (ti.com) (SOC Initialization Using SD BOOT section) for details.

    Best regards,

    Ming

  • I put mcu_plus_sdk_am64x_08_01_00_36\tools\boot\sbl_prebuilt\am64x-evm\sbl_null.release.tiimage onto the SD card, and re-named it as tiboot3.bin. I installed the SD card, change the switches to the SD boot setting, and powered the development board. I got the following messages on the terminal:

    Starting NULL Bootloader ...

    DMSC Firmware Version 21.9.0--v2021.09 (Terrific Llam
    DMSC Firmware revision 0x15
    DMSC ABI revision 3.1

    INFO: Bootloader_runCpu:150: CPU r5f1-0  is initialized to 800000000 Hz !!!
    INFO: Bootloader_runCpu:150: CPU r5f1-1 is initialized to 800000000 Hz !!!
    INFO: Bootloader_runCpu:150: CPU m4f0-0 is initialized to 400000000 Hz !!!
    INFO: Bootloader_runCpu:150: CPU a530-0 is initialized to 800000000 Hz !!!
    INFO: Bootloader_runCpu:150: CPU a530-1 is initialized to 800000000 Hz !!!
    INFO: Bootloader_loadSelfCpu:202: CPU r5f0-0 is initialized to 800000000 Hz !!!
    INFO: Bootloader_loadSelfCpu:202: CPU r5f0-1 is initialized to 800000000 Hz !!!
    INFO: Bootloader_runSelfCpu:219: All done, reseting self ...

    I did not see any messages about DDR. Did it actually initialize the DDR?

    Thanks for your help,

    Paul

  • Hi Paul,

    Yes, it does the DDR initialization. After the UART display the above message, you should be able to use the JTAG connect to the R5_0_0 core without using GEL file or launch.js. Once JTAG is connected to R5_0-0, you should be able to access the DDR (0x80000000) in the CCS Memory Browser. No need to run any GEL script.

    Best regards,

    Ming