AM2434: GPMC speed

PhoenixPrototype_nortos.zipI was not able to attach the code in the original post. Here is the code. Thank you.

Hi Leo,

GMPC driver is not currently supported for AM243x MCU+ SDK. If you have to use the GPMC, you will need to write your own GPMC driver for AM243x. The TRM has the details of how to configure the GPMC for different usage.

Your problem most likely is caused by the GPMC_FCLK. There are two possible input clock sources for it: MAIN_PLL0_HSDIV3_CLKO and MAIN_PLL2_HSDIV7_CLKO. I see you used MAIN_PLL2_HSDIV7_CLKO in your code. According to the AM243x gel file (CCS 11.1.0), the MAIN_PLL2_HSDIV7_CLKO was set to 100Mhz ("//PLL2: Peripheral 1 PLL" in AM24_PLL_PARAMS_OFC1.gel). MAIN_PLL0_HSDIV3_CLKO was set to 250Mhz ("/PLL0: Main PLL" in AM24_PLL_PARAMS_OFC1.gel). If you are using the GEL file to set your PLLs, then try to use the MAIN_PLL0_HSDIV3_CLKO instead of MAIN_PLL2_HSDIV7_CLKO. Hopefully you can get 25Mhz maximum speed. If this works, then you can further change MAIN_PLL0_HSDIV3_CLKO or MAIN_PLL2_HSDIV7_CLKO to higher frequency and in turn to get higher maximum GPMC speed.

Best regards,

Ming

Hi,

Thank you for your quick answer. I configured the PLL0_HSDIV3_CLKO with the following configuration : 

Reference Divider : 2

Feedback Divider : 384

Output divider #1 : 1

Output divider #2 : 2

HSDIV3 Divider : 2

With this configuration I should get a clock at (((25M / 2) * 384) / 2) / 2 = 1.2GHz. At this frequency, I should be able to communicate at 100MHz, but in my main loop the STORE instruction does not go faster than 5 MHz at the output of the GPMC... Is there another clock I should configure? Like the bus clock? Or should I write the GPMC through the DMA to get a better speed?

Here is the update of my code : 0250.PhoenixPrototype_nortos.zip

Thank you,

Leo

This is an addition to my previous post. I have made a simple test where I took to the example udma_memcpy_polling_am243x-evm_r5fss0-0_freertos_ti-arm-clang and replace the destination buffer by the GPMC write address. I was able to go much faster than 5 MHz. I would still prefer to control the GPMC from one of the R5F core. I guess that the problem is from the bus or the arbitration that allows the write action to the GPMC. Is there a way to increase the priority of the read/write action on the GMPC by the core?

Thank you,

Leo

Hi Leo,

Can you use the old code and still use the CCS GEL to set up the PLLs? Just change to PLL0_HSDIV3_CLKO? This way, we can rule out the possible PLL setting issue.

Best regards,

Ming

Hi Ming,

I did not figure out how to program the PLL via the GEL file... When I modify the #define MAIN_PLL1_OFC1_HSDIV3_DIV_VAL in the AM24_PLL_PARAMS_OFC1.gel file, I do not see the new value I entered at the end of the boot in the registers. I modify the gel file in the following directory : C:\ti\ccs1110\ccs\ccs_base\emulation\gel\AM24x\AM24_PLL\25MHz_HFOSC. Is there something I missed? I am still new to the GEL files and how they work in CCS.

Thank you,

Leo

Hi Leo,

You should have changed the  MAIN_PLL0_OFC1_HSDIV3_DIV_VAL (not  MAIN_PLL1_OFC1_HSDIV3_DIV_VAL). 

In C:\ti\ccs1110\ccs\ccs_base\emulation\gel\AM24x\AM24_PLL\25MHz_HFOSC\AM24_PLL_PARAMS_OFC1.gel

//PLL0: Main PLL
/* Frequencies:

PLL input: 25MHz
VCO output: 2GHz
POSTDIV output: 1GHz
HSDIV0 output: 500MHz
HSDIV1 output: 200MHz
HSDIV2 output: 80MHz
HSDIV3 output: 133.33MHz
HSDIV4 output: 250MHz
HSDIV5 output: 200MHz
HSDIV6 output: 250MHz
HSDIV7 output: 250MHz
HSDIV8 output: 125MHz
HSDIV9 output: 333.33MHz
MODSS configuration:
- Spread: 3.125%
- Modulator Divider: %-by-1
- Downspread or centerspread: downspread

*/
#define MAIN_PLL0_OFC1_FBDIV 80 //fbdiv
#define MAIN_PLL0_OFC1_FRACDIV -1 //fracdiv
#define MAIN_PLL0_OFC1_PREDIV 1 //prediv
#define MAIN_PLL0_OFC1_POSTDIV1 2 //postdiv1
#define MAIN_PLL0_OFC1_POSTDIV2 1 //postdiv2
#define MAIN_PLL0_OFC1_HSDIV0_DIV_VAL 3 //4
#define MAIN_PLL0_OFC1_HSDIV1_DIV_VAL 9 //10
#define MAIN_PLL0_OFC1_HSDIV2_DIV_VAL 24 //25
#define MAIN_PLL0_OFC1_HSDIV3_DIV_VAL 14 //15
#define MAIN_PLL0_OFC1_HSDIV4_DIV_VAL 7 //8
#define MAIN_PLL0_OFC1_HSDIV5_DIV_VAL 4 //5
#define MAIN_PLL0_OFC1_HSDIV6_DIV_VAL 3 //4
#define MAIN_PLL0_OFC1_HSDIV7_DIV_VAL 3 //4
#define MAIN_PLL0_OFC1_HSDIV8_DIV_VAL 7 //8
#define MAIN_PLL0_OFC1_HSDIV9_DIV_VAL 2 //3
#define MAIN_PLL0_OFC1_SSMOD_SPREAD 0x1F //spread
#define MAIN_PLL0_OFC1_SSMOD_MODDIV -1 //mod_div
#define MAIN_PLL0_OFC1_SSMOD_DOWNSPREAD 1 //downspread

2000Mhz/15 = 133.33Mhz

If you change the MAIN_PLL0_OFC1_HSDIV3_DIV_VAL from 14 to 9, then it will be 2000Mhz/10 = 200Mhz.

Best regards,

Ming