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Original question:

VIM

TMS570LS3137: Why interrupts don't work when VIC port is enable?

Juan Carlos Aguirre
Prodigy 80 points
Part Number: TMS570LS3137


Hi
I'm working with the initial configuration sequence for the microcontroller; I'm using as guide SPNA106D. There is a step that indicate to enable de VIC Port in the CPU registers, but still having doubts about the functionality of that port, also I have a problem when I enable the VIC Port, the interrupts doesn't works when is enable and works when is disable (btw I'm using a OS that manage the installation of the interrupt handlers).


So my questions are, what is the deferens between work with the VIC port enabled or disabled?
And what could be a possible reason that explain that when is enabled the interrupts doesn't work?

Thanks.

  • 0
    TI__Mastermind 29808 points

    Hi, our expert is out of office until 4/7. Please expect a delayed response.
    Also, please see this FAQ: software-dl.ti.com/.../index.html

  • 0 in reply to Frank Livingston
    TI__Guru**** 198986 points

    Hi,

    When CPU receives a IRQ, CPU reads the address of ISR directly from the interface with VIM (VIC port) instead of branching to 0x18. The CPU will branch directly to the ISR.

    There are three different ways to react on interrupts:

    1. Legacy ARM7 Mode: In this mode the software designer has to write a software dispatcher for the FIQ and IRQ.
    2. Vectored interrupt: In this mode the VIM module dose the dispatching for IRQ and FIQ and has an register which shows the address of the pending interrupts routine. The CPU has to load the vector address to the PC via a LDR instruction.
    3. Hardware Vectored Interrupt: This mode is only available for IRQ. In this mode the VIM dose the dispatching and supplies the vector address to the Cortex-R4F CPU via the VIC Port. This mode is similar to #2 but it saves the load instruction on address 0x18 and thus a few cycles.
  • 0 in reply to QJ Wang
    Prodigy 80 points

    Hi, Thanks for you answer, I have a doubt, if I'm using the VIM option, isn't necessary to modify the state of the VE bit in the CPU register to enabled VIC port functionality? 

  • +1 in reply to Juan Carlos Aguirre
    TI__Guru**** 198986 points

    Hi Juan,

    The VIM is required for both vector INT and HW vector INT (VIC is enabled). You don't have to enable the VIC port. 

    When an event occurs within a peripheral, the peripheral makes an interrupt request to the VIM. Then, VIM prioritizes the requests from peripherals and generates the vector corresponding to the highest active IRQ, then it updates the FIQINDEX or the IRQINDEX register, depending on the class of interrupt. Then, it accesses the interrupt vector table using the vector value to fetch the address of the corresponding ISR. If the request is an FIQ class interrupt, the address read from the interrupt vector table, is written to the FIQVECREG register. If the request is an IRQ class interrupt, the address is written to the IRQVECREG register and put on the VIC port of the CPU (in case of hardware vectored interrupt is enabled). All of the interrupt registers are updated when a new high priority interrupt line becomes active.

    If the OS supports Vector Interrupt mode, the HW vector interrupt should be supported too.