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How to find out interrupt destination of hardwired interrupts.

Other Parts Discussed in Thread: SYSCONFIG

Hello,
I am currently programming on an AM243x using the MCU+ SDK.

In the past I had asked some questions about interrupt routing,
where the TI guys where a great help.

Now I also want to configure the hardwired interrupts.
For this purpose I will be using the functionality in kernel/dpl/HwiP.h.

There it says:

/**
 * \brief Parameters passed during \ref HwiP_construct
 */
typedef struct HwiP_Params_ {

    uint32_t intNum;   /**< CPU interrupt number. */
    HwiP_FxnCallback callback; /**< Callback to call when interrupt is received */
    void *args; /**< Arguments to pass to the callback */
    uint16_t eventId; /**< Event ID to register against, only used with c6x with event combiner */
    uint8_t priority; /**< Interrupt priority, only used with ARM R5, ARM M4 */
    uint8_t isFIQ; /**< 0: Map interrupt as ISR, 1: map interrupt as FIQ, only used with ARM R5 */
    uint8_t isPulse; /**< 0: Map interrupt as level interrupt, 1: Map interrupt as pulse interrupt, only used with ARM R5, ARM M4 */

} HwiP_Params;


So, there are some parameters that only apply to a specific MCU.
Especially I would like to use the priorities and the FIQs, as my current concern is having maskable and non-maskable interrupts of different priority.

Here I would like to fail with an ASSERT for instance if an interrupt is set as FIQ but the destination interrupt controller is not the VIM of the R5F-MCU.
But I don't see any way to find out to which destination interrupt controller an interrupt line with the provided IRQ number is connected,
except for the user reading the information from the schematics and providing it as an extra parameter (which could also be a wrong input, which makes the whole assertion obsolete).

I thought I could use HwiP_Config to check at least if the intcBaseAddr is set to that of the R5F-VIM, as said in the comments:

/**
 * \brief HwiP config parameters, setup as part of SysConfig, not to be set by end-users directly
 */
typedef struct HwiP_Config_
{
    uint32_t intcBaseAddr; /**< For R5F, this is VIM base addr */

} HwiP_Config;


to find out if my destination is the R5F-VIM.
But I don't know how to get the HwiP_Config out of the constructed HwiP_Object.
Thank you for your help.

Best regards


Philip.

  • Hi Philip,

    As of the interrupts directly connected to the R5F core VIM, you can find the corresponding interrupt numbers in C:\ti\mcu_plus_sdk_am243x_08_02_00_31\source\drivers\hw_include\am64x_am243x\cslr_intr_r5fss0_core0.h. For example MAIN domain UART0 interrupt is CSLR_R5FSS0_CORE0_INTR_UART0_USART_IRQ_0 (210). Timer8 (used by Clock in example.syscfg) interrupt is CSLR_R5FSS0_CORE0_INTR_TIMER8_INTR_PEND_0 (160).

    Best regards,

    Ming

  • Hello Ming,
    thank you for your answer.
    But there seems to be a misunderstanding.
    The intended question was not how I, as a human being, could find out the right interrupt numbers for a specific MCU looking into some document.
    The question was, how given a specific HwiP-configuration can my program automatically find out to which MCU/interrupt controller the interrupt line is connected.
    My first guess would be, that it should be in the default_boardConfiguration resasg-entries somewhere, but I am not sure about that and if yes, then where.
    Thank you for your help.


    Best regards

    Philip.

  • It seems that the VIM base address is set in dpl_config.c, which is generated by SysConfig.
    But the gHwiConfig, which holds this address is only generated when I make a syscfg-file for the R5.
    It does not exist at all if I make one for the M4.
    Maybe I am lacking C/C++ skills, but I find it rather hard to check if a global variable exists at all.

    It would be way easier if the variable simply had a different value for the M4.
    Doesn't it also have a base address? I cannot find anything about an NVIC base address in the TRM.
    Thank you for your help.

  • Hi Philip,

    As you mentioned in your post for R5F, it uses VIM. Its base address is 0x2FFF0000 defined in gHwiConfig and used in C:\ti\mcu_plus_sdk_am243x_08_02_00_31\source\kernel\nortos\dpl\r5\HwiP_armv7r_vim.c. For M4F, it uses NVIC. Its base address is 0xE000E000 (table 2-5 in TRM) defined in C:\ti\mcu_plus_sdk_am243x_08_02_00_31\source\kernel\nortos\dpl\m4\HwiP_armv7m.h. It is used in C:\ti\mcu_plus_sdk_am243x_08_02_00_31\source\kernel\nortos\dpl\m4\HwiP_armv7m.c in the forms of NVIC_ISER, NVIC_ICER etc.

    I know it is a little bit inconsistent, but that is the way it has been implemented in the DPL. For the interrupt number for each interrupt source, you can find the definitions in C:\ti\mcu_plus_sdk_am243x_08_02_00_31\source\drivers\hw_include\am64x_am243x\cslr_intr_mcu_m4fss0_core0.h, in case you may need them.

    Best regards,

    Ming

  • Hello Ming,
    thank you for those informations, I also found those yesterday



    But sadly my problem still remains. Even if I know how those base addresses should be in the HwiP_Config.intcBaseAddr,
    I am not aware how to obtain the HwiP_Config having only the HwiP_Params-structure and the HwiP_Object after execution of HwiP_construct.

    What I need is something like for instance:

    HwiP_Config* HwiP_getConfig(HwiP_Object * constructedObject);

    Then I can compare the addresses to find out what the destination interrupt controller is.
    Thank you for your help.


    Best regards

    Philip.

  • Hi Philip,

    Here is what I did:

    1. Imported the hello_world_am243x-evm_m4fss0-0_nortos_ti-arm-clang, then added a Timer using the SysConfig (example.syscfg):

    2. After build the project, open the generated file ti_dpl_config.c, the TimerP_init has the HwiP_Params_init and HwiP_construct for set up the HWI for the MCU Timer 0:

    Best regards,

    Ming

  • Hello Ming,
    thank you for your answer, but I am not sure what to do with it.
    Are you sure, the answer was not ment for the following question:

    https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1097178/mcu-plus-sdk-am243x-how-to-do-hw-timers-in-mcu-sdk

    I am not sure, how your answer would help me find out what the destination interrupt controller for a hardwired interrupt line would be.
    Thank you for your help.


    Best regards

    Philip.

  • HI Philip,

    After 

    status = HwiP_construct(&gTimerHwiObj[CONFIG_TIMER0], &timerHwiParams);

    you can use 

    HwiP_getConfig(&gTimerHwiObj[CONFIG_TIMER0]);

    to get what you need.

    Best regards,

    Ming

  • Hello Ming,
    thank you for your answer.
    Maybe I am blind, but in my code neither I nor the find function of CCS finds any function called HwiP_getConfig.

    What I wrote in my question above is that I would need a function like this:



    I never said, that there is such a function, so if indeed there is such a function, please tell me where to find it.
    Thank you for your help.


    Best regards

    Philip.

  • Also, I still don't know what you would like to show me concerning those timers.
    I don't work with timers at all.


    Best regards

    Philip.

  • Hi Philip,

    Sorry, I did not understand your question in the first place. What you really interested to know is the priority and the FIQ for each interrupt. The FIQ is only available for the R5F core, while the priority is for R5F and M4F.

    In this case, I would suggest you to use the Core ID to do the checking, instead of using the base address of the interrupt controller (VIM or NVIC). Currently there is no API for you to get the self Core ID, but you can use the method the IPC example is using in ipc_notify_echo.c

    /* main core that starts the message exchange */
    uint32_t gMainCoreId = CSL_CORE_ID_R5FSS0_0;

    If you really want to identify the self core ID on fly, I think there is a ARM core register which can tell you the cluster and core number, but you will have to read and interpret the register value by your self.

    Best regards,

    Ming

  • Hello Ming,
    I am not sure if I want the self Core ID. That depends on if the destination of any hardwired interrupt always is the same core where the origin of the interrupt lies.

    If otherwise a hardwired (not using the interrupt router or aggregator) interrupt could have its origin within one hosts subsystem but the destination being another hosts subsystem, then what I would like is to get the core ID or host ID of the destination, not the origin.
    Thank you for your help.


    Best regards

    Philip.

  • Hello Ming,
    it seems there was a bit of confusion on my part.
    What I really want to know is the destination interrupt controller before having an HwiP_object.

    What I am still not understanding is where the information of the destination interrupt controller comes in at all.

    For instance looking at the interrupt maps in the TRM, let's look at for instance IRQ number 22 (just a random number):











    So to configure an interrupt, I have the following parameters:



    Assuming I want to have an interrupt configuration for all the above interrupts with IRQ number 22 from the TRM,
    and I want to set a different ISR for each one of them,
    how would I know which ISR would be set to which one of them?

    I cannot see any parameter where I actually tell the HwiP what destination interrupt controller I am aiming for.
    And the intNum alone is ambigous (it is 22 for all the above cases).

    Thank you for your help, and sorry for the confusion.


    Best regards

    Philip.



  • Hi Philip,

    As we discussed in the call, it is all depending on where the HwiP_construct() get called. If it is called on R5F cores, then the HwiP_construct in C:\ti\mcu_plus_sdk_am243x_08_02_00_31\source\kernel\nortos\dpl\r5\HwiP_armv7r_vim.c get called, so the HwiP_setAsFIQ() is used. If it is called on M4F core, then the HwiP_construct in C:\ti\mcu_plus_sdk_am243x_08_02_00_31\source\kernel\nortos\dpl\m4\HwiP_armv7m.c get called, where the HwiP_setAsFIQ() is not used. The same should apply to the ICSS case (although there is no prebuilt ICSSG DPL library yet). Ultimately different DPL library will be linked to the application running on different cores.

    You abstract HWI class can either use the same HwiP_construct(), then later on link to different DPL library, or you want to implement the HwiP from scratch in your own HWI class (although I would not recommend this way)

    Best regards,

    Ming

  • Hello Ming,
    thank you for the fast response.
    So, as I understand it from your explanation, it would not be possible to configure interrupts destined for let's say the M4 in an initialization routine (calling the HwiP_construct) that runs on the R5. Is that correct?
    Thank you for your help.


    Best regards

    Philip.

  • Hi Philip,

    That is correct. The HwiP_construct() only sets the interrupt controller for the core where the HwiP_construct()is called.

    Best regards,

    Ming 

  • Thank you for clarification.


    Best regards

    Philip.