RM48L952: Error handling for DCAN RX over DMA

The error generated by IF3x will trigger the error interrupt too, and the flag bit in ES register will be set, and int0ID is set to 0x8000.

The status of IF3x read is observed by the status flag in IF3OBS register.

How can I configure DMA to store ES register and int0ID together with IF3MSK, IF3ARB, IF3MCTL and IF3DATx registers?

Hi Eduard,

Why do you transfer the data from IF3ARB, IF3MSK, and IF3MCTL, and ES register to system memory through DMA? Normally we use DMA to transfer data from IF3DATx to system memory, and the status register is checked by CPU. 

I have to transfer message ID or errors to higer level software. The reason I want to use DMA instead of CAN interrupts is a problem with the order of received messages. As described here: e2e.ti.com/.../dcan-fifo-reading-while-receiving

So I wanted to transfer messages over DMA to a buffer and read them from the buffer in timer interrupt

Am I missing something important?

Ok, nice knowing your idea. You can use separate DMA channels for IF3ARB, IF3MSK, IF3MCTL, and DCAN ES, and DCAN INT.

The DMA transfer for DCAN ES, and DCAN INT has to be triggered by software. 

Which advantage do i have using separate DMA channels? 

The DCAN ES is at 0x4 (offset), DCAN INT is at 0x10, and IF3xMSK/ARM/MCTL/DataA/DataB are at 0x144, 0x148, 0x14C, 0x150, 0x154. If you use one DMA channel, how do you map those register addresses to the DMA configuration (source address, offset, etc)?

May be I understood the errata sheet of RM57 microcontroller wrong, but i thought that to avoid the receive message order problem, DMA should be used instead of can interrupts.So I disabled CAN interrupts an enabled only IF3 register DMA transfer.  Could you please send me an example code that solves receive message order problem?

Eduard Mustafin said:

Could you please send me an example code that solves receive message order problem?

What does "message order problem" mean? RM48L952 is a little endian device, there is no byte-order issue. 

RM57 is also a little endian device and it has an errata sheet entry for Silicon Revision B: DCAN#27 During DCAN FIFO Mode, received messages may be placed out of order in the FIFO buffer

I am facing the same issue with RM48. I receive 100 messages with the same id and sometimes the order of messages is not correct. Normally two consequent messages are placed in memory in reversed order. It happens when I use IF1 and IF2 registers. 

Hi Eduard,

The errata is only applied to RM57 which operates in DCAN FIFO mode. Do you use FIFO mode?

Yes

I don't see the advantage to use FIFO mode for IF3x interface. As mentioned before, IF3x can automatically receive control and user data from the Message RAM when a message object has been updated after reception of a CAN message, and the DMA request is generated automatically for transferring data from IF3x register set to the buffers in SRAM. The CPU does not need to initiate the transfer from Message RAM to IF3 register set.

For FIFO mode, the CPU has to initiate the transfer from FIFO in Message RAM to IF3 register set, and trigger the DMA manually to transfer data from IF3x registers to buffers in SRAM. 

About FIFO mode, let me add more comments:

FIFO can be used for RX data frame and TX data frame. Since remote frame doesn't contain data field, FIFO is not used for remote frame, but receive objects for Remote Frames can use a FIFO buffer.

FIFO mode allows you to receive a group of frames with the same ID (or same ID after filtering) and only generate an interrupt to the CPU when the last one comes in. Setup a block of mailboxes with the same identifier and mask. For example, if the most bytes you need to receive in this group is 64, then configure 8 mailboxes with the same identifier and mask. For example let's use mailboxes 1-8. The first 7 (1-7) set EoB (end of buffer) to 0 and RxIE (receive interrupt enable) to 0. On the eighth mailbox set EoB to 1 and RxIE to 1.

Now let's assume that one of the nodes needs to send 24 bytes. It sends the first two frame with EoB=0 and the third frame with EoB=1. The first two frames end up in mailboxes 1 and 2, the third frame ends up in mailbox 8 and generates an interrupt. In the interrupt routine for mailbox 8, since you know it is the end of a FIFO, you start reading from mailbox 1. You must check the NewDat bit of each mailbox as you read it. When you hit mailbox 3, NewDat=0, so you can now skip to mailbox 8 and read the last frame from the group.

When one of the nodes needs to send 24 bytes, how does it indicate the value of EoB flag in messages? 

I have problems receiving, not transmitting. And I use FIFO for RX messages. Not for particular ID, but for any ID. I don't know IDs in advance.  

Eduard Mustafin said:

When one of the nodes needs to send 24 bytes, how does it indicate the value of EoB flag in messages? 

I thought you are using FIFO for transmitting.

Eduard Mustafin said:

Not for particular ID, but for any ID.

As I mentioned before, FIFO mode allows you to receive a group of frames with the same ID and only generate an interrupt to the CPU when the last one comes in. The FIFO or the message object does not accept a frame with a different message ID.