AM2634-Q1: Can QSPI memory-map reads external Flash in 16/32 or even 64-bit?

    // QSPI configuration
    CSL_QspiRegs * qspi_regs_struct = (CSL_QspiRegs *)CSL_QSPI0_U_BASE ;
    qspi_regs_struct->SPI_SWITCH_REG = CSL_QSPI_SPI_SWITCH_REG_MMPT_S_SEL_CFG_PORT ;   // configure SPI_CORE
    // SPI Clock generator
    qspi_regs_struct->SPI_CLOCK_CNTRL_REG = (qspi_regs_struct->SPI_CLOCK_CNTRL_REG &
            (~CSL_QSPI_SPI_CLOCK_CNTRL_REG_DCLK_DIV_MASK)) | 0U ;   // 80 MHz
    qspi_regs_struct->SPI_CLOCK_CNTRL_REG |= CSL_QSPI_SPI_CLOCK_CNTRL_REG_CLKEN_MASK ;
    // SPI Clock polarity and phase modes 3 (or 0)
    qspi_regs_struct->SPI_DC_REG = qspi_regs_struct->SPI_DC_REG | CSL_QSPI_SPI_DC_REG_CKP0_MASK
            | CSL_QSPI_SPI_DC_REG_CKPH0_MASK ;

    // SFI configuration
    qspi_regs_struct->SPI_SETUP0_REG = (CSL_QSPI_SPI_SETUP0_REG_RCMD_MASK & 0x6CU) |
            (0x3U << CSL_QSPI_SPI_SETUP0_REG_NUM_A_BYTES_SHIFT) |
            (0x1U << CSL_QSPI_SPI_SETUP0_REG_NUM_D_BYTES_SHIFT) |
            (CSL_QSPI_SPI_SETUP0_REG_READ_TYPE_QUAD_READ << CSL_QSPI_SPI_SETUP0_REG_READ_TYPE_SHIFT) |
            (0x8U << CSL_QSPI_SPI_SETUP0_REG_NUM_D_BITS_SHIFT ) ;

    qspi_regs_struct->SPI_SWITCH_REG = CSL_QSPI_SPI_SWITCH_REG_MMPT_S_SEL_MM_PORT ;

    readFlash = *((uint32_t *)0x60000000) ;

static int32_t QSPI_spiMemMapRead(QSPI_Handle handle)
{
    /* Destination address */
    uint32_t *pDst = NULL;
    /* Source address */
    uint32_t *pSrc = NULL;
    /* Transaction length */
    uint32_t count;
    /* Memory mapped command */
    uint32_t mmapReadCmd;
    uintptr_t temp_addr;
    uintptr_t offset;
    int32_t status = SystemP_SUCCESS;
    uint32_t dummyBytes, dummyBits;

    if(handle != NULL)
    {
        QSPI_Attrs const  *attrs = ((QSPI_Config *)handle)->attrs;
        QSPI_Object  *object = ((QSPI_Config *)handle)->object;
        QSPI_Transaction *transaction = object->transaction;
        const CSL_QspiRegs *pReg = (const CSL_QspiRegs *)attrs->baseAddr;

        /* Get flash offset */
        offset = (uintptr_t)transaction->addrOffset;

        /* Extract memory map mode read command */
        mmapReadCmd = (uint32_t)object->readCmd;

        /* Set the number of address bytes  */
        CSL_REG32_FINS((&pReg->SPI_SETUP0_REG)+(attrs->chipSelect * 0x4U),
                    QSPI_SPI_SETUP0_REG_NUM_A_BYTES, (object->numAddrBytes - 1));

        dummyBytes = object->numDummyBits / 8U;
        dummyBits = object->numDummyBits % 8U;

        CSL_REG32_FINS((&pReg->SPI_SETUP0_REG)+(attrs->chipSelect * 0x4U),
                        QSPI_SPI_SETUP0_REG_NUM_D_BITS, dummyBits);
        CSL_REG32_FINS((&pReg->SPI_SETUP0_REG)+(attrs->chipSelect * 0x4U),
                        QSPI_SPI_SETUP0_REG_NUM_D_BYTES, dummyBytes);
        CSL_REG32_FINS((&pReg->SPI_SETUP0_REG)+(attrs->chipSelect * 0x4U),
                        QSPI_SPI_SETUP0_REG_RCMD, mmapReadCmd);

        switch(object->rxLines)
        {
            case QSPI_RX_LINES_SINGLE:
            {
                CSL_REG32_FINS((&pReg->SPI_SETUP0_REG)+(attrs->chipSelect * 0x4U),
                    QSPI_SPI_SETUP0_REG_READ_TYPE, QSPI_MEM_MAP_READ_TYPE_NORMAL);
                break;
            }

            case QSPI_RX_LINES_DUAL:
            {
                CSL_REG32_FINS((&pReg->SPI_SETUP0_REG)+(attrs->chipSelect * 0x4U),
                    QSPI_SPI_SETUP0_REG_READ_TYPE, QSPI_MEM_MAP_READ_TYPE_DUAL);
                break;
            }

            case QSPI_RX_LINES_QUAD:
            {
                CSL_REG32_FINS((&pReg->SPI_SETUP0_REG)+(attrs->chipSelect * 0x4U),
                    QSPI_SPI_SETUP0_REG_READ_TYPE, QSPI_MEM_MAP_READ_TYPE_QUAD);
                break;
            }

            default:
            break;
        }
        temp_addr = ((uintptr_t)attrs->memMapBaseAddr + (uintptr_t)transaction->addrOffset);
        pSrc = ((uint32_t *)(temp_addr));
        pDst = (uint32_t *)transaction->buf;
        count = transaction->count;

        if (attrs->dmaEnable == true)
        {
            QSPI_edmaTransfer(pDst, pSrc, count, handle);
        }
        else
        {
            while(count > 0)
            {
                /* Do the normal memory to memory transfer. Copy will be in bytes */
                *pDst = *pSrc;
                pDst++;
                pSrc++;
                count -= 4;
            }
        }
    }
    else
    {
        status = SystemP_FAILURE;
    }
    return status;
}

    int32_t status;

    Bootloader_profileReset();
    Bootloader_socConfigurePll();
    Bootloader_socInitL2MailBoxMemory();

    System_init();
    Bootloader_profileAddProfilePoint("System_init");

    *((uint32_t *) (0x50D00800)) = 0x3U ;