TMS570LC4357: TMS570LC4357: FLA12 Idle State Parity Test continued

Hi Max,

Max Wittekind said:

(Q1)I am confused. Why should the CPU Interconnect Subsystem be used to specificaly test Idle Parity of Flash (We do that seperatly)?

We select the parity checker using FPAR_OVR. The parity scheme is inverted, and the checker will generate the parity which is reported to ESM and Flash status register.

The parity error can also be triggered using SCM. 

Max Wittekind said:

(Q2) Is the FPAR_OVR Register of the Flash not designed to execute parity Testing by selecting a Parity by setting PAR_OVR_SEL and then triggering the Test by setting PAR_OVR_KEY?

FPAR_OVR is designed for parity testing.

Max Wittekind said:

Q3) Can you please provide a full description of the FLA12 diagnostic?

We select the parity checker using PAR_OVR:

1. idle state parity checker

2. command parity checker

3. internal  address parity checker

This is my test:

void ParityTest_Flash()
{
//Flash Parity Diagnostic test
sl_flashWREG->FPAR_OVR = 0x15A00; //idle state parity check; ESM 2.17; PortAErrStatus=0x4000
readValue = *(uint32_t *)0x00000000;
sl_esmREG->SR1[1] = 0x00020000;
sl_esmREG->SSR2 = 0x20000;
sl_flashWREG->FEDAC_PASTATUS = 0x4000; //Parity error is detected in idle state.

sl_flashWREG->FPAR_OVR = 0x25A00; //Command parity checker; ESM 3.13, PortAErrStatus=0x400
readValue = *(uint32_t *)0x00000000;
sl_esmREG->SR1[2] = 0x00002000; //address parity error/internal parity error
sl_flashWREG->FEDAC_PASTATUS = 0x400; //Address Parity Error Flag.

sl_flashWREG->FPAR_OVR = 0x35A00; //Internal address parity checker; ESM 3.13, PortAErrStatus=0x400
readValue = *(uint32_t *)0x00000000;
sl_esmREG->SR1[2] = 0x00002000; //address parity error/internal parity error
sl_flashWREG->FEDAC_PASTATUS = 0x400; //Address Parity Error Flag.

sl_flashWREG->FPAR_OVR = 0x05400;
sl_flashWREG->FEDAC_PASTATUS = 0xFFFFFFFF;
sl_esmREG->SR1[1] = 0xFFFFFFFF;
sl_esmREG->SR1[2] = 0xFFFFFFFF;
sl_esmREG->SSR2 = 0xFFFFFFFF;
}