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Hi experts,
We implemented the FLA12 Test of parity Logic. But when we try to test the idle state parity, nothing happens.
We tried what was suggested here: e2e.ti.com/.../tms570lc4357-flash-parity-override-register-how-to-set-a-port-to-idle-state PAR_OVR_KEY#
But even with Diag Mode 7 and Test Mode enabled nothing happens:
What we tried:
volatile uint32_t flashRead; /* Enable diagnostic mode and select diag mode 7 */ /* DIAG_BUF_SEL [10:8] [10:8] = 0 : Port A selected to flip data/ECC */ /* DIAG_BUF_SEL = 4: Port B selected to flip data/ECC */ flashWREG->FDIAGCTRL = 0x00050007U; flashWREG->FPAR_OVR = 0x00010000U; /* enables the parity checking on the access */ flashWREG->FPAR_OVR |= 0x00005A00U; flashRead = *(volatile uint32_t *) 0x00000008U; /* disable diagnostic mode */ flashWREG->FDIAGCTRL = 0x000A0007U;
(Q1) When running this code, nothing happens. Can you me tell what we are doing wrong?
Thank you and best regards,
Max
Hi Max,
You can perform the parity diag test by writing 0xA to PAR DIAG EN of SCMCNTL register.
Hi QJ,
(Q2)I am confused. Why should the CPU Interconnect Subsystem be used to specificaly test Idle Parity of Flash?
(Q3) Is the FPAR_OVR Register of the Flash not designed to execute parity Testing by selecting a Parity by setting PAR_OVR_SEL and then triggering the Test by setting PAR_OVR_KEY?